Searched refs:CGU_CLK_DIV (Results 1 – 9 of 9) sorted by relevance
| /linux/drivers/clk/ingenic/ |
| A D | jz4770-cgu.c | 151 "cclk", CGU_CLK_DIV,
159 "h0clk", CGU_CLK_DIV,
167 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
176 "h2clk", CGU_CLK_DIV,
184 "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
193 "pclk", CGU_CLK_DIV,
225 "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
232 "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
239 "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
270 "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
[all …]
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| A D | jz4740-cgu.c | 95 "pll half", CGU_CLK_DIV,
104 "cclk", CGU_CLK_DIV,
113 "hclk", CGU_CLK_DIV,
122 "pclk", CGU_CLK_DIV,
131 "mclk", CGU_CLK_DIV,
140 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
150 "lcd_pclk", CGU_CLK_DIV,
156 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
164 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
172 "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
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| A D | jz4760-cgu.c | 145 "cclk", CGU_CLK_DIV,
153 "hclk", CGU_CLK_DIV,
161 "sclk", CGU_CLK_DIV,
169 "h2clk", CGU_CLK_DIV,
177 "mclk", CGU_CLK_DIV,
185 "pclk", CGU_CLK_DIV,
196 "pll0_half", CGU_CLK_DIV,
257 "i2s", CGU_CLK_DIV | CGU_CLK_MUX,
274 "mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV,
280 "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
[all …]
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| A D | jz4725b-cgu.c | 80 "pll half", CGU_CLK_DIV,
89 "cclk", CGU_CLK_DIV,
98 "hclk", CGU_CLK_DIV,
107 "pclk", CGU_CLK_DIV,
116 "mclk", CGU_CLK_DIV,
125 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
135 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
142 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
150 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
158 "mmc_mux", CGU_CLK_DIV,
[all …]
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| A D | jz4780-cgu.c | 343 "cpu", CGU_CLK_DIV,
349 "l2cache", CGU_CLK_DIV,
355 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
370 "ahb2", CGU_CLK_DIV,
376 "pclk", CGU_CLK_DIV,
382 "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
398 "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
433 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
440 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
447 "msc2", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
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| A D | x1000-cgu.c | 253 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
260 "l2cache", CGU_CLK_DIV,
266 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
279 "ahb2", CGU_CLK_DIV,
285 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
292 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
300 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
308 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
322 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
329 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
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| A D | x1830-cgu.c | 227 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
234 "l2cache", CGU_CLK_DIV,
240 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
253 "ahb2", CGU_CLK_DIV,
259 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
266 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
274 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
283 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
299 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
306 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
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| A D | cgu.c | 391 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
478 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
510 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
668 if (caps & CGU_CLK_DIV) { in ingenic_register_clock()
669 caps &= ~CGU_CLK_DIV; in ingenic_register_clock()
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| A D | cgu.h | 159 CGU_CLK_DIV = BIT(5), enumerator
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