| /linux/drivers/gpu/drm/radeon/ |
| A D | rv740d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| A D | rv730d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| A D | rs780d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| A D | rs780_dpm.c | 212 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv()
987 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_debugfs_print_current_performance_level()
1009 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_get_current_sclk()
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| A D | r600_dpm.c | 322 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
324 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
332 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) in r600_wait_for_spll_change()
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| A D | rv740_dpm.c | 288 RREG32(CG_SPLL_FUNC_CNTL); in rv740_read_clock_registers()
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| A D | rv730_dpm.c | 200 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
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| A D | rv770d.h | 89 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| A D | si.c | 3986 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
3988 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
4017 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4019 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4021 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4023 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
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| A D | nid.h | 538 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| A D | sid.h | 85 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| A D | cikd.h | 248 #define CG_SPLL_FUNC_CNTL 0xC0500140 macro
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| A D | evergreend.h | 74 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| A D | r600d.h | 1270 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| A D | rv770_dpm.c | 1523 RREG32(CG_SPLL_FUNC_CNTL); in rv770_read_clock_registers()
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| A D | ni_dpm.c | 1183 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in ni_read_clock_registers()
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| A D | ci_dpm.c | 1838 RREG32_SMC(CG_SPLL_FUNC_CNTL); in ci_read_clock_registers()
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| A D | si_dpm.c | 3552 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | si.c | 1334 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
1336 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
1365 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
1367 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
1369 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
1371 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
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| A D | sid.h | 86 #define CG_SPLL_FUNC_CNTL 0x180 macro
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| A D | fiji_smumgr.c | 885 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
887 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
1343 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
1345 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
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| A D | iceland_smumgr.c | 826 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in iceland_calculate_sclk_params()
828 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in iceland_calculate_sclk_params()
1462 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in iceland_populate_smc_acpi_level()
1464 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in iceland_populate_smc_acpi_level()
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| A D | ci_smumgr.c | 326 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
328 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
1415 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in ci_populate_smc_acpi_level()
1417 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in ci_populate_smc_acpi_level()
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| A D | tonga_smumgr.c | 569 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
1210 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
1212 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/ |
| A D | si_dpm.c | 4011 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
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