Searched refs:CG_SPLL_FUNC_CNTL_3 (Results 1 – 19 of 19) sorted by relevance
| /linux/drivers/gpu/drm/radeon/ |
| A D | rv740d.h | 37 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
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| A D | rv730d.h | 40 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
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| A D | rv740_dpm.c | 292 RREG32(CG_SPLL_FUNC_CNTL_3); in rv740_read_clock_registers()
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| A D | rv730_dpm.c | 204 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
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| A D | rv770d.h | 104 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
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| A D | nid.h | 550 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
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| A D | sid.h | 99 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
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| A D | cikd.h | 260 #define CG_SPLL_FUNC_CNTL_3 0xC0500148 macro
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| A D | evergreend.h | 86 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
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| A D | rv770_dpm.c | 1527 RREG32(CG_SPLL_FUNC_CNTL_3); in rv770_read_clock_registers()
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| A D | ni_dpm.c | 1185 ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); in ni_read_clock_registers()
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| A D | ci_dpm.c | 1842 RREG32_SMC(CG_SPLL_FUNC_CNTL_3); in ci_read_clock_registers()
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| A D | si_dpm.c | 3554 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); in si_read_clock_registers()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| A D | fiji_smumgr.c | 891 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3, in fiji_calculate_sclk_params()
895 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3, in fiji_calculate_sclk_params()
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| A D | iceland_smumgr.c | 832 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); in iceland_calculate_sclk_params()
836 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1); in iceland_calculate_sclk_params()
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| A D | ci_smumgr.c | 332 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3, in ci_calculate_sclk_params()
336 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3, in ci_calculate_sclk_params()
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| A D | tonga_smumgr.c | 575 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); in tonga_calculate_sclk_params()
579 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1); in tonga_calculate_sclk_params()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | sid.h | 100 #define CG_SPLL_FUNC_CNTL_3 0x182 macro
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| /linux/drivers/gpu/drm/amd/pm/powerplay/ |
| A D | si_dpm.c | 4013 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); in si_read_clock_registers()
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