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Searched refs:CKSEG1ADDR (Results 1 – 25 of 42) sorted by relevance

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/linux/arch/mips/include/asm/
A Dsni.h40 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
46 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)
49 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)
52 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)
56 #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054)
65 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c)
67 #define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c)
71 #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084)
80 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0000)
83 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018)
[all …]
A Daddrspace.h74 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) macro
81 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) macro
A Dvga.h19 #define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
A Dbarrier.h56 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
/linux/arch/mips/dec/prom/
A Didentify.c74 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn01()
82 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn230()
91 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC); in prom_init_kn02()
100 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn02xa()
101 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn02xa()
110 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn03()
111 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn03()
/linux/arch/mips/dec/
A Decc-berr.c144 (void *)CKSEG1ADDR(address); in dec_ecc_be_backend()
227 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in dec_kn02_be_init()
229 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); in dec_kn02_be_init()
230 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); in dec_kn02_be_init()
245 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in dec_kn03_be_init()
246 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn03_be_init()
248 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR); in dec_kn03_be_init()
249 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN); in dec_kn03_be_init()
A Dkn02xa-berr.c29 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_ack()
30 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); in dec_kn02xa_be_ack()
40 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_backend()
41 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); in dec_kn02xa_be_backend()
126 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn02xa_be_init()
A Dkn02-irq.c30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq()
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq()
62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs()
A Dkn01-berr.c49 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_ack()
62 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + in dec_kn01_be_backend()
150 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_interrupt()
177 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_init()
A Dint-handler.S30 #define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
31 #define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
32 #define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
A Dreset.c17 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000); in back_to_prom()
/linux/arch/mips/boot/compressed/
A Duart-16550.c13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
18 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
23 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
/linux/arch/mips/lib/
A Duncached.c48 usp = CKSEG1ADDR(sp); in run_uncached()
60 ufunc = CKSEG1ADDR(lfunc); in run_uncached()
/linux/drivers/mtd/devices/
A Dms02-nv.c88 ms02nv_diagp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_DIAG)); in ms02nv_probe_one()
89 ms02nv_magicp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_MAGIC)); in ms02nv_probe_one()
277 csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in ms02nv_init()
283 csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in ms02nv_init()
/linux/arch/mips/cobalt/
A Dsetup.c84 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); in plat_mem_setup()
118 setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); in prom_init()
A Dreset.c20 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
A Dpci.c38 .io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),
/linux/arch/mips/sgi-ip22/
A Dip22-gio.c276 ptr32 = (void *)CKSEG1ADDR(addr); in ip22_gio_id()
286 ptr8 = (void *)CKSEG1ADDR(addr + 3); in ip22_gio_id()
297 ptr16 = (void *)CKSEG1ADDR(addr + 2); in ip22_gio_id()
318 ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS); in ip22_is_gr2()
/linux/arch/mips/fw/sni/
A Dsniprom.c35 #define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)
87 return (void *)CKSEG1ADDR(hwconf); in prom_get_hwconf()
/linux/arch/mips/generic/
A Dboard-sead3.c19 #define SEAD_CONFIG CKSEG1ADDR(0x1b100110)
22 #define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
/linux/arch/mips/include/asm/mach-cobalt/
A Dmach-gt64120.h12 #define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
/linux/arch/mips/kernel/
A Dsmp-cps.c108 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); in cps_smp_setup()
224 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); in boot_core()
325 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); in cps_boot_secondary()
/linux/arch/mips/loongson64/
A Dsmp.c797 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); in play_dead()
805 (void *)CKSEG1ADDR((unsigned long)loongson3_type1_play_dead); in play_dead()
810 (void *)CKSEG1ADDR((unsigned long)loongson3_type2_play_dead); in play_dead()
817 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); in play_dead()
/linux/drivers/net/ethernet/amd/
A Ddeclance.c1069 dev->base_addr = CKSEG1ADDR(dec_kn_slot_base + IOASIC_LANCE); in dec_lance_probe()
1075 dev->mem_start = CKSEG1ADDR(0x00020000); in dec_lance_probe()
1078 esar_base = CKSEG1ADDR(dec_kn_slot_base + IOASIC_ESAR); in dec_lance_probe()
1125 dev->mem_start = CKSEG1ADDR(start); in dec_lance_probe()
1154 dev->base_addr = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE); in dec_lance_probe()
1155 dev->mem_start = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE_MEM); in dec_lance_probe()
1157 esar_base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_ESAR + 1); in dec_lance_probe()
/linux/arch/mips/sni/
A Drm200.c415 #define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000)
416 #define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000)

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