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Searched refs:CLKID_FCLK_DIV3 (Results 1 – 17 of 17) sorted by relevance

/linux/include/dt-bindings/clock/
A Daxg-clkc.h14 #define CLKID_FCLK_DIV3 3 macro
A Dmeson8b-clkc.h13 #define CLKID_FCLK_DIV3 6 macro
A Dgxbb-clkc.h13 #define CLKID_FCLK_DIV3 5 macro
A Dg12a-clkc.h14 #define CLKID_FCLK_DIV3 3 macro
/linux/Documentation/devicetree/bindings/clock/
A Damlogic,axg-audio-clkc.txt46 <&clkc CLKID_FCLK_DIV3>,
/linux/arch/arm64/boot/dts/amlogic/
A Dmeson-g12.dtsi83 <&clkc CLKID_FCLK_DIV3>,
A Dmeson-sm1.dtsi181 <&clkc CLKID_FCLK_DIV3>,
A Dmeson-gxbb.dtsi753 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
A Dmeson-gxl.dtsi822 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
A Dmeson-axg.dtsi1312 <&clkc CLKID_FCLK_DIV3>,
A Dmeson-g12-common.dtsi1680 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
/linux/arch/arm/boot/dts/
A Dmeson8.dtsi710 <&clkc CLKID_FCLK_DIV3>,
A Dmeson8b.dtsi702 <&clkc CLKID_FCLK_DIV3>,
/linux/drivers/clk/meson/
A Dmeson8b.c2781 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2989 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3208 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
A Dgxbb.c2699 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
2911 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
A Dg12a.c4252 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4481 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4745 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
A Daxg.c1898 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,

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