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Searched refs:CLKID_VCLK_DIV6 (Results 1 – 8 of 8) sorted by relevance

/linux/include/dt-bindings/clock/
A Daxg-clkc.h90 #define CLKID_VCLK_DIV6 125 macro
A Dg12a-clkc.h116 #define CLKID_VCLK_DIV6 151 macro
A Dgxbb-clkc.h137 #define CLKID_VCLK_DIV6 188 macro
/linux/drivers/clk/meson/
A Dmeson8b.h132 #define CLKID_VCLK_DIV6 146 macro
A Dmeson8b.c2920 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3128 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3347 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
A Dgxbb.c2877 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
3088 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
A Dg12a.c4401 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4630 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4894 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
A Daxg.c2019 [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,

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