| /linux/include/dt-bindings/clock/ |
| A D | mt8167-clk.h | 17 #define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0) macro
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| A D | mt8135-clk.h | 114 #define CLK_APMIXED_TVDPLL 7 macro
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| A D | mt6797-clk.h | 113 #define CLK_APMIXED_TVDPLL 6 macro
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| A D | mt8173-clk.h | 163 #define CLK_APMIXED_TVDPLL 8 macro
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| A D | mt2712-clk.h | 22 #define CLK_APMIXED_TVDPLL 10 macro
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| A D | mt6779-clk.h | 176 #define CLK_APMIXED_TVDPLL 11 macro
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| A D | mt8183-clk.h | 19 #define CLK_APMIXED_TVDPLL 8 macro
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| A D | mt2701-clk.h | 180 #define CLK_APMIXED_TVDPLL 6 macro
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| A D | mt8192-clk.h | 308 #define CLK_APMIXED_TVDPLL 7 macro
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| /linux/Documentation/devicetree/bindings/display/mediatek/ |
| A D | mediatek,dpi.yaml | 81 <&apmixedsys CLK_APMIXED_TVDPLL>;
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8135.c | 620 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
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| A D | clk-mt6797.c | 647 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
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| A D | clk-mt2701.c | 947 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
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| A D | clk-mt8167.c | 1031 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0x00000001, 0,
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| A D | clk-mt6779.c | 1200 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
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| A D | clk-mt8173.c | 982 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
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| A D | clk-mt8183.c | 1144 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
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| A D | clk-mt8192.c | 1172 PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000,
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| A D | clk-mt2712.c | 1245 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
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| /linux/arch/arm/boot/dts/ |
| A D | mt7623n.dtsi | 228 <&apmixedsys CLK_APMIXED_TVDPLL>;
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8173.dtsi | 1244 <&apmixedsys CLK_APMIXED_TVDPLL>;
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