Searched refs:CLK_BDP_WR_DI_PXL (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/clk/mediatek/ | ||
| A D | clk-mt2701-bdp.c | 72 GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26), |
| /linux/include/dt-bindings/clock/ | ||
| A D | mt2701-clk.h | 458 #define CLK_BDP_WR_DI_PXL 27 macro |
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