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Searched refs:CLK_DIVIDER_ONE_BASED (Results 1 – 25 of 30) sorted by relevance

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/linux/drivers/clk/zynq/
A Dclkc.c138 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_register_fclk()
143 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_register_fclk()
281 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
325 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
338 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
342 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
393 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
418 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
446 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
450 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
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/linux/drivers/clk/loongson1/
A Dclk-loongson1b.c62 CLK_DIVIDER_ONE_BASED | in ls1x_clk_init()
79 DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); in ls1x_clk_init()
95 DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, in ls1x_clk_init()
A Dclk-loongson1c.c57 CLK_DIVIDER_ONE_BASED | in ls1x_clk_init()
66 DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); in ls1x_clk_init()
/linux/drivers/clk/mmp/
A Dclk-mmp2.c337 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
368 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
391 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
410 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
438 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
A Dclk-audio.c268 priv->sysclk_div.flags = CLK_DIVIDER_ONE_BASED; in register_clocks()
289 priv->sspa0_div.flags = CLK_DIVIDER_ONE_BASED; in register_clocks()
320 priv->sspa1_div.flags = CLK_DIVIDER_ONE_BASED; in register_clocks()
A Dclk-mix.c33 if (mix->div_flags & CLK_DIVIDER_ONE_BASED) in _get_maxdiv()
50 if (mix->div_flags & CLK_DIVIDER_ONE_BASED) in _get_div()
87 if (mix->div_flags & CLK_DIVIDER_ONE_BASED) in _get_div_val()
A Dclk-of-mmp2.c350 …{0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0…
352 …{0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1…
A Dclk-of-pxa1928.c155 {0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock},
/linux/drivers/clk/ti/
A Ddivider.c55 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
70 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
92 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_val()
506 div->flags |= CLK_DIVIDER_ONE_BASED; in ti_clk_divider_populate()
A Dadpll.c662 CLK_DIVIDER_ONE_BASED); in ti_adpll_init_children_adpll_s()
705 CLK_DIVIDER_ONE_BASED); in ti_adpll_init_children_adpll_s()
735 CLK_DIVIDER_ONE_BASED); in ti_adpll_init_children_adpll_lj()
/linux/drivers/staging/clocking-wizard/
A Dclk-xlnx-clock-wizard.c511 flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED | in clk_wzrd_probe()
536 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in clk_wzrd_probe()
545 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in clk_wzrd_probe()
/linux/drivers/clk/
A Dclk-divider.c71 if (flags & CLK_DIVIDER_ONE_BASED) in _get_maxdiv()
94 if (flags & CLK_DIVIDER_ONE_BASED) in _get_div()
119 if (flags & CLK_DIVIDER_ONE_BASED) in _get_val()
A Dclk-asm9260.c311 base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED, in asm9260_acc_init()
A Dclk-bm1880.c686 div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; in bm1880_clk_register_div()
833 div_hws->div.flags = CLK_DIVIDER_ONE_BASED | in bm1880_clk_register_composite()
A Dclk-nomadik.c538 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in of_nomadik_hclk_setup()
A Dclk-stm32h7.c1175 M_CFG_DIV(NULL, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
1256 base + RCC_CFGR, 8, 6, CLK_DIVIDER_ONE_BASED | in stm32h7_rcc_init()
/linux/drivers/clk/mxs/
A Dclk-div.c93 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
/linux/arch/powerpc/platforms/512x/
A Dclock-commonclk.c759 CLK_DIVIDER_ONE_BASED); in mpc512x_clk_setup_clock_tree()
763 9, 7, CLK_DIVIDER_ONE_BASED); in mpc512x_clk_setup_clock_tree()
769 CLK_DIVIDER_ONE_BASED); in mpc512x_clk_setup_clock_tree()
/linux/drivers/clk/sunxi/
A Dclk-a10-pll2.c66 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in sun4i_pll2_setup()
/linux/drivers/clk/imx/
A Dclk-divider-gate.c207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_hw_divider_gate()
/linux/drivers/clk/nxp/
A Dclk-lpc32xx.c936 if (flags & CLK_DIVIDER_ONE_BASED) in _get_div()
1280 CLK_DIVIDER_ONE_BASED),
1286 CLK_DIVIDER_ONE_BASED),
1333 LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED),
/linux/drivers/clk/zynqmp/
A Ddivider.c298 ccf_flag |= CLK_DIVIDER_ONE_BASED; in zynqmp_clk_map_divider_ccf_flags()
/linux/drivers/gpu/drm/msm/dsi/phy/
A Ddsi_phy_10nm.c605 0, 4, CLK_DIVIDER_ONE_BASED, in pll_10nm_register()
669 4, 4, CLK_DIVIDER_ONE_BASED, in pll_10nm_register()
A Ddsi_phy_7nm.c631 0, 4, CLK_DIVIDER_ONE_BASED, in pll_7nm_register()
711 4, 4, CLK_DIVIDER_ONE_BASED, in pll_7nm_register()
/linux/drivers/clk/xilinx/
A Dxlnx_vcu.c441 u8 divider_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | in xvcu_clk_hw_register_leaf()

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