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Searched refs:CLK_FIN_PLL (Results 1 – 20 of 20) sorted by relevance

/linux/Documentation/devicetree/bindings/timer/
A Dsamsung,exynos4210-mct.yaml79 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
99 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
120 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
140 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
/linux/include/dt-bindings/clock/
A Dexynos5410.h13 #define CLK_FIN_PLL 1 macro
A Dexynos5250.h13 #define CLK_FIN_PLL 1 macro
A Dexynos4.h15 #define CLK_FIN_PLL 3 macro
A Dexynos5420.h13 #define CLK_FIN_PLL 1 macro
A Dexynos3250.h26 #define CLK_FIN_PLL 2 macro
/linux/Documentation/devicetree/bindings/arm/samsung/
A Dpmu.yaml127 clocks = <&clock CLK_FIN_PLL>;
/linux/arch/arm/boot/dts/
A Dexynos3250.dtsi179 clocks = <&cmu CLK_FIN_PLL>;
230 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
231 <&cmu CLK_FIN_PLL>;
282 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
A Dexynos5250.dtsi241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
250 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
295 clocks = <&clock CLK_FIN_PLL>;
660 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
691 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
A Dexynos5420.dtsi187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
838 clocks = <&clock CLK_FIN_PLL>;
1304 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
A Dexynos4210.dtsi125 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
A Dexynos5250-snow-common.dtsi672 assigned-clock-parents = <&clock CLK_FIN_PLL>;
A Dexynos4412.dtsi268 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
A Dexynos4.dtsi70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
A Dexynos5800-peach-pi.dts931 assigned-clock-parents = <&clock CLK_FIN_PLL>;
A Dexynos5420-peach-pit.dts949 assigned-clock-parents = <&clock CLK_FIN_PLL>;
/linux/drivers/clk/samsung/
A Dclk-exynos5250.c225 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
A Dclk-exynos3250.c234 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
A Dclk-exynos4.c1054 fclk.id = CLK_FIN_PLL; in exynos4_clk_register_finpll()
A Dclk-exynos5420.c445 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),

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