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Searched refs:CLK_MM_DISP_SPLIT1 (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/clk/mediatek/
A Dclk-mt8173-mm.c76 GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
/linux/include/dt-bindings/clock/
A Dmt8173-clk.h276 #define CLK_MM_DISP_SPLIT1 29 macro
/linux/arch/arm64/boot/dts/mediatek/
A Dmt8173.dtsi1197 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;

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