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Searched refs:CLK_MUX_HIWORD_MASK (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/clk/hisilicon/
A Dclk-hi3670.c420 0xAC, 0, 1, CLK_MUX_HIWORD_MASK, },
444 0xAC, 4, 1, CLK_MUX_HIWORD_MASK, },
447 0xAC, 3, 1, CLK_MUX_HIWORD_MASK, },
450 0xAC, 2, 1, CLK_MUX_HIWORD_MASK, },
456 0xAC, 8, 1, CLK_MUX_HIWORD_MASK, },
459 0xb4, 5, 1, CLK_MUX_HIWORD_MASK, },
465 0xC8, 8, 4, CLK_MUX_HIWORD_MASK, },
468 0xC8, 4, 4, CLK_MUX_HIWORD_MASK, },
785 0x74, 6, 4, CLK_MUX_HIWORD_MASK, },
788 0x68, 6, 4, CLK_MUX_HIWORD_MASK, },
[all …]
A Dclk-hi3660.c271 CLK_MUX_HIWORD_MASK, },
274 CLK_MUX_HIWORD_MASK, },
277 CLK_MUX_HIWORD_MASK, },
280 CLK_MUX_HIWORD_MASK, },
283 CLK_MUX_HIWORD_MASK, },
286 CLK_MUX_HIWORD_MASK, },
289 CLK_MUX_HIWORD_MASK, },
292 CLK_MUX_HIWORD_MASK, },
295 CLK_MUX_HIWORD_MASK, },
298 CLK_MUX_HIWORD_MASK, },
[all …]
A Dclk-hi3620.c96 … uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, },
97 … uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, },
98 … uart2_mux_p, ARRAY_SIZE(uart2_mux_p), CLK_SET_RATE_PARENT, 0x100, 9, 1, CLK_MUX_HIWORD_MASK, },
99 … uart3_mux_p, ARRAY_SIZE(uart3_mux_p), CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, },
100 … uart4_mux_p, ARRAY_SIZE(uart4_mux_p), CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, },
101 … spi0_mux_p, ARRAY_SIZE(spi0_mux_p), CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, },
102 … spi1_mux_p, ARRAY_SIZE(spi1_mux_p), CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, },
103 … spi2_mux_p, ARRAY_SIZE(spi2_mux_p), CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, },
104 … saxi_mux_p, ARRAY_SIZE(saxi_mux_p), CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, },
105 … pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, },
[all …]
A Dclk-hi6220.c156 …fi_src, ARRAY_SIZE(hifi_src), CLK_SET_RATE_PARENT, 0x400, 0, 1, CLK_MUX_HIWORD_MASK,},
157 …rt1_src, ARRAY_SIZE(uart1_src), CLK_SET_RATE_PARENT, 0x400, 1, 1, CLK_MUX_HIWORD_MASK,},
158 …rt2_src, ARRAY_SIZE(uart2_src), CLK_SET_RATE_PARENT, 0x400, 2, 1, CLK_MUX_HIWORD_MASK,},
159 …rt3_src, ARRAY_SIZE(uart3_src), CLK_SET_RATE_PARENT, 0x400, 3, 1, CLK_MUX_HIWORD_MASK,},
160 …rt4_src, ARRAY_SIZE(uart4_src), CLK_SET_RATE_PARENT, 0x400, 4, 1, CLK_MUX_HIWORD_MASK,},
161 …c0_mux0_p, ARRAY_SIZE(mmc0_mux0_p), CLK_SET_RATE_PARENT, 0x400, 5, 1, CLK_MUX_HIWORD_MASK,},
162 …c1_mux0_p, ARRAY_SIZE(mmc1_mux0_p), CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,},
163 …c2_mux0_p, ARRAY_SIZE(mmc2_mux0_p), CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,},
164 …c0_mux1_p, ARRAY_SIZE(mmc0_mux1_p), CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,},
165 …c1_mux1_p, ARRAY_SIZE(mmc1_mux1_p), CLK_SET_RATE_PARENT, 0x400, 14, 1, CLK_MUX_HIWORD_MASK,},
[all …]
/linux/drivers/clk/
A Dclk-mux.c111 if (mux->flags & CLK_MUX_HIWORD_MASK) { in clk_mux_set_parent()
163 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { in __clk_hw_register_mux()
/linux/drivers/clk/rockchip/
A Dclk-muxgrf.c44 if (mux->flags & CLK_MUX_HIWORD_MASK) in rockchip_muxgrf_set_parent()
A Dclk-rk3036.c145 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-rk3128.c169 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-rk3228.c179 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-rk3188.c237 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-rk3328.c232 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-rv1108.c162 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-pll.c894 pll_mux->flags |= CLK_MUX_HIWORD_MASK; in rockchip_clk_register_pll()
A Dclk-rk3368.c151 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-rk3288.c245 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-px30.c204 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-rk3308.c194 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-rk3399.c240 #define MFLAGS CLK_MUX_HIWORD_MASK
A Dclk-rk3568.c335 #define MFLAGS CLK_MUX_HIWORD_MASK
/linux/drivers/clk/zynqmp/
A Dclk-mux-zynqmp.c109 ccf_flag |= CLK_MUX_HIWORD_MASK; in zynqmp_clk_map_mux_ccf_flags()
/linux/drivers/clk/ti/
A Dmux.c81 if (mux->flags & CLK_MUX_HIWORD_MASK) { in ti_clk_mux_set_parent()
/linux/drivers/clk/renesas/
A Dr9a07g044-cpg.c126 sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
/linux/include/linux/
A Dclk-provider.h879 #define CLK_MUX_HIWORD_MASK BIT(2) macro

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