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Searched refs:CLK_MUX_READ_ONLY (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/clk/zynqmp/
A Dclk-mux-zynqmp.c111 ccf_flag |= CLK_MUX_READ_ONLY; in zynqmp_clk_map_mux_ccf_flags()
146 if (nodes->type_flag & CLK_MUX_READ_ONLY) in zynqmp_clk_register_mux()
/linux/drivers/clk/nxp/
A Dclk-lpc32xx.c1114 .ops = (_flags & CLK_MUX_READ_ONLY ? \
1236 CLK_MUX_READ_ONLY),
1238 CLK_MUX_READ_ONLY),
1240 CLK_MUX_READ_ONLY),
1243 CLK_MUX_READ_ONLY),
1245 CLK_MUX_READ_ONLY),
1327 LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY),
A Dclk-lpc18xx-cgu.c223 LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY),
/linux/drivers/clk/rockchip/
A Dclk-half-divider.c186 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops in rockchip_clk_register_halfdiv()
A Dclk.c66 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops in rockchip_clk_register_branch()
A Dclk-rk3568.c522 RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
525 RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
/linux/drivers/clk/renesas/
A Dr9a07g044-cpg.c105 sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
/linux/drivers/clk/
A Dclk-mux.c177 if (clk_mux_flags & CLK_MUX_READ_ONLY) in __clk_hw_register_mux()
A Dclk-stm32mp1.c910 element->mux.flags = CLK_MUX_READ_ONLY; in clk_register_pll()
/linux/drivers/clk/samsung/
A Dclk-s3c64xx.c125 MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
A Dclk-s5pv210.c370 CLK_MUX_READ_ONLY, 0),
/linux/drivers/clk/imx/
A Dclk.h183 …x_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
/linux/drivers/pinctrl/tegra/
A Dpinctrl-tegra20.c2241 pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL); in tegra20_pinctrl_register_clock_muxes()
2244 pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL); in tegra20_pinctrl_register_clock_muxes()
/linux/include/linux/
A Dclk-provider.h880 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ macro

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