Searched refs:CLK_MUX_READ_ONLY (Results 1 – 14 of 14) sorted by relevance
/linux/drivers/clk/zynqmp/ |
A D | clk-mux-zynqmp.c | 111 ccf_flag |= CLK_MUX_READ_ONLY; in zynqmp_clk_map_mux_ccf_flags() 146 if (nodes->type_flag & CLK_MUX_READ_ONLY) in zynqmp_clk_register_mux()
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/linux/drivers/clk/nxp/ |
A D | clk-lpc32xx.c | 1114 .ops = (_flags & CLK_MUX_READ_ONLY ? \ 1236 CLK_MUX_READ_ONLY), 1238 CLK_MUX_READ_ONLY), 1240 CLK_MUX_READ_ONLY), 1243 CLK_MUX_READ_ONLY), 1245 CLK_MUX_READ_ONLY), 1327 LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY),
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A D | clk-lpc18xx-cgu.c | 223 LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY),
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/linux/drivers/clk/rockchip/ |
A D | clk-half-divider.c | 186 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops in rockchip_clk_register_halfdiv()
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A D | clk.c | 66 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops in rockchip_clk_register_branch()
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A D | clk-rk3568.c | 522 RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 525 RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
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/linux/drivers/clk/renesas/ |
A D | r9a07g044-cpg.c | 105 sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
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/linux/drivers/clk/ |
A D | clk-mux.c | 177 if (clk_mux_flags & CLK_MUX_READ_ONLY) in __clk_hw_register_mux()
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A D | clk-stm32mp1.c | 910 element->mux.flags = CLK_MUX_READ_ONLY; in clk_register_pll()
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/linux/drivers/clk/samsung/ |
A D | clk-s3c64xx.c | 125 MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
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A D | clk-s5pv210.c | 370 CLK_MUX_READ_ONLY, 0),
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/linux/drivers/clk/imx/ |
A D | clk.h | 183 …x_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
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/linux/drivers/pinctrl/tegra/ |
A D | pinctrl-tegra20.c | 2241 pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL); in tegra20_pinctrl_register_clock_muxes() 2244 pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL); in tegra20_pinctrl_register_clock_muxes()
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/linux/include/linux/ |
A D | clk-provider.h | 880 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ macro
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