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Searched refs:CLK_OPS_PARENT_ENABLE (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/clk/qcom/
A Dlpass-gfm-sm8250.c75 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
95 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
115 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
135 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
155 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
175 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
A Dgcc-sm6115.c729 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
752 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
767 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
782 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
804 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
819 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
834 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
849 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1038 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1060 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
[all …]
A Dgpucc-sdm660.c118 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
A Dgpucc-msm8998.c148 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
A Dgcc-qcm2290.c790 .flags = CLK_OPS_PARENT_ENABLE,
805 .flags = CLK_OPS_PARENT_ENABLE,
820 .flags = CLK_OPS_PARENT_ENABLE,
835 .flags = CLK_OPS_PARENT_ENABLE,
989 .flags = CLK_OPS_PARENT_ENABLE,
A Dcamcc-sc7180.c734 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
A Dgcc-sc7280.c996 .flags = CLK_OPS_PARENT_ENABLE,
/linux/drivers/clk/imx/
A Dclk.h159 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
165 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
171 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
186 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
193 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE)
373 (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
A Dclk-imx7d.c709 …root_clk", "ahb_root_clk", base + 0x9080, 0, 2, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE | CLK_SET_… in imx7d_clocks_init()
773 …= imx_clk_hw_gate2_flags("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0, CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
775 …gs("main_axi_root_clk", "axi_post_div", base + 0x4040, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
780 …flags("dram_root_clk", "dram_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
781 …s("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
782 …lt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
783 …ram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
A Dclk-imx8mq.c574 …_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); in imx8mq_clocks_probe()
576 …_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); in imx8mq_clocks_probe()
582 …lags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); in imx8mq_clocks_probe()
A Dclk-imx7ulp.c108 …, base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); in imx7ulp_clk_scg1_init()
/linux/drivers/clk/mediatek/
A Dclk-mt8195-imp_iic_wrap.c21 &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
A Dclk-mt8192-imp_iic_wrap.c23 &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
/linux/drivers/clk/
A Dclk-stm32mp1.c1358 COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
1802 MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
1805 MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
1809 CLK_OPS_PARENT_ENABLE,
1815 CLK_OPS_PARENT_ENABLE,
2020 COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
2027 COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
2033 COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
2039 COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
2049 COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
A Dclk.c1249 if (core->flags & CLK_OPS_PARENT_ENABLE) in clk_disable_unused_subtree()
1281 if (core->flags & CLK_OPS_PARENT_ENABLE) in clk_disable_unused_subtree()
1794 if (core->flags & CLK_OPS_PARENT_ENABLE) { in __clk_set_parent_before()
1827 if (core->flags & CLK_OPS_PARENT_ENABLE) { in __clk_set_parent_after()
2102 if (core->flags & CLK_OPS_PARENT_ENABLE) in clk_change_rate()
2119 if (core->flags & CLK_OPS_PARENT_ENABLE) in clk_change_rate()
3135 ENTRY(CLK_OPS_PARENT_ENABLE),
/linux/drivers/clk/xilinx/
A Dxlnx_vcu.c540 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE); in xvcu_register_clock_provider()
/linux/include/linux/
A Dclk-provider.h32 #define CLK_OPS_PARENT_ENABLE BIT(12) macro
/linux/drivers/clk/rockchip/
A Dclk-rk3568.c546 …_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,

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