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Searched refs:CLK_PERI_PWM5 (Results 1 – 11 of 11) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmt8135-clk.h164 #define CLK_PERI_PWM5 26 macro
A Dmt8173-clk.h200 #define CLK_PERI_PWM5 7 macro
A Dmt2712-clk.h246 #define CLK_PERI_PWM5 7 macro
A Dmt2701-clk.h228 #define CLK_PERI_PWM5 7 macro
/linux/Documentation/devicetree/bindings/pwm/
A Dpwm-mediatek.txt43 <&pericfg CLK_PERI_PWM5>;
/linux/drivers/clk/mediatek/
A Dclk-mt8135.c485 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
A Dclk-mt2701.c848 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
A Dclk-mt8173.c687 GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
A Dclk-mt2712.c1080 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
/linux/arch/arm64/boot/dts/mediatek/
A Dmt2712e.dtsi487 <&pericfg CLK_PERI_PWM5>,
/linux/arch/arm/boot/dts/
A Dmt7623.dtsi430 <&pericfg CLK_PERI_PWM5>;

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