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Searched refs:CLK_PWM0 (Results 1 – 18 of 18) sorted by relevance

/linux/Documentation/devicetree/bindings/pwm/
A Dpwm-sprd.txt27 clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
31 assigned-clocks = <&aon_clk CLK_PWM0>,
/linux/arch/arm/boot/dts/
A Dpxa27x.dtsi50 clocks = <&clks CLK_PWM0>;
64 clocks = <&clks CLK_PWM0>;
A Dpxa25x.dtsi68 clocks = <&clks CLK_PWM0>;
A Dpxa3xx.dtsi225 clocks = <&clks CLK_PWM0>;
241 clocks = <&clks CLK_PWM0>;
/linux/include/dt-bindings/clock/
A Dpxa-clock.h47 #define CLK_PWM0 37 macro
A Dactions,s500-cmu.h43 #define CLK_PWM0 23 macro
A Dactions,s700-cmu.h66 #define CLK_PWM0 43 macro
A Dactions,s900-cmu.h68 #define CLK_PWM0 50 macro
A Dsprd,sc9863a-clk.h120 #define CLK_PWM0 15 macro
A Dsprd,sc9860-clk.h124 #define CLK_PWM0 18 macro
A Drk3568-cru.h26 #define CLK_PWM0 13 macro
/linux/arch/arm64/boot/dts/rockchip/
A Drk356x.dtsi269 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
280 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
291 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
302 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
/linux/drivers/clk/actions/
A Dowl-s500.c496 [CLK_PWM0] = &pwm0_clk.common.hw,
A Dowl-s700.c532 [CLK_PWM0] = &clk_pwm0.common.hw,
A Dowl-s900.c663 [CLK_PWM0] = &pwm0_clk.common.hw,
/linux/drivers/clk/rockchip/
A Dclk-rk3568.c1501 COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0,
/linux/drivers/clk/sprd/
A Dsc9863a-clk.c789 [CLK_PWM0] = &pwm0_clk.common.hw,
A Dsc9860-clk.c721 [CLK_PWM0] = &pwm0_clk.common.hw,

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