Searched refs:CLK_SCLK_MMC0 (Results 1 – 21 of 21) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | exynos5410.h | 26 #define CLK_SCLK_MMC0 132 macro
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| A D | exynos5250.h | 35 #define CLK_SCLK_MMC0 139 macro
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| A D | exynos7-clk.h | 61 #define CLK_SCLK_MMC0 8 macro
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| A D | exynos4.h | 58 #define CLK_SCLK_MMC0 145 macro
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| A D | exynos5420.h | 33 #define CLK_SCLK_MMC0 132 macro
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| A D | exynos3250.h | 249 #define CLK_SCLK_MMC0 241 macro
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| A D | exynos5433.h | 570 #define CLK_SCLK_MMC0 63 macro
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| /linux/drivers/clk/samsung/ |
| A D | clk-exynos5410.c | 172 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
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| A D | clk-exynos5250.c | 475 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
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| A D | clk-exynos3250.c | 550 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
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| A D | clk-exynos7.c | 534 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
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| A D | clk-exynos4.c | 767 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
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| A D | clk-exynos5420.c | 1006 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
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| A D | clk-exynos5433.c | 2319 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
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| /linux/arch/arm/boot/dts/ |
| A D | exynos5410.dtsi | 132 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
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| A D | exynos3250.dtsi | 382 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
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| A D | exynos4.dtsi | 323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
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| A D | exynos5250.dtsi | 548 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
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| A D | exynos5420.dtsi | 210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
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| /linux/arch/arm64/boot/dts/exynos/ |
| A D | exynos7.dtsi | 561 <&clock_top1 CLK_SCLK_MMC0>;
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| A D | exynos5433.dtsi | 1829 <&cmu_fsys CLK_SCLK_MMC0>;
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Completed in 47 milliseconds