Searched refs:CLK_SCLK_MPLL (Results 1 – 5 of 5) sorted by relevance
| /linux/arch/arm/boot/dts/ |
| A D | exynos4210-trats.dts | 216 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
224 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
232 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
240 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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| A D | exynos4210-universal_c210.dts | 231 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
239 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
247 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
255 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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| A D | exynos4210-i9100.dts | 313 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
322 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
330 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
339 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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| /linux/include/dt-bindings/clock/ |
| A D | exynos4.h | 21 #define CLK_SCLK_MPLL 9 macro
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| /linux/drivers/clk/samsung/ |
| A D | clk-exynos4.c | 463 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
540 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
1308 hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200, in exynos4_clk_init()
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