Home
last modified time | relevance | path

Searched refs:CLK_SET_PARENT_GATE (Results 1 – 25 of 28) sorted by relevance

12

/linux/drivers/clk/imx/
A Dclk-imx7d.c501 …_mux2_flags("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
512 …_mux2_flags("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
513 …_mux2_flags("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
514 …_mux2_flags("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
521 …_hw_mux2_flags("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
522 …_mux2_flags("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
523 …_mux2_flags("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
527 …_mux2_flags("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
528 …_mux2_flags("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
529 …_mux2_flags("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel), CLK_SET_PARENT_GATE); in imx7d_clocks_init()
[all …]
A Dclk-imx7ulp.c73 …s("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
74 …s("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
97 …0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
98 …0x608, 14, 2, spll_pfd_sels, ARRAY_SIZE(spll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
99 …, base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
100 …, base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
A Dclk-imx8ulp.c167 …("spll2_pre_sel", base + 0x510, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx8ulp_clk_cgc1_init()
168 …("spll3_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx8ulp_clk_cgc1_init()
249 …s("pll4_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx8ulp_clk_cgc2_init()
254 …w_mux_flags("hifi_sel", base + 0x14, 28, 3, hifi_sels, ARRAY_SIZE(hifi_sels), CLK_SET_PARENT_GATE); in imx8ulp_clk_cgc2_init()
258 …k_hw_mux_flags("ddr_sel", base + 0x40, 28, 3, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_PARENT_GATE); in imx8ulp_clk_cgc2_init()
A Dclk-composite-7ulp.c144 CLK_SET_PARENT_GATE | CLK_SET_RATE_NO_REPARENT); in imx_ulp_clk_hw_composite()
A Dclk-composite-8m.c220 flags |= CLK_SET_PARENT_GATE; in __imx8m_clk_hw_composite()
/linux/drivers/clk/qcom/
A Dgcc-msm8660.c128 .flags = CLK_SET_PARENT_GATE,
179 .flags = CLK_SET_PARENT_GATE,
230 .flags = CLK_SET_PARENT_GATE,
281 .flags = CLK_SET_PARENT_GATE,
332 .flags = CLK_SET_PARENT_GATE,
383 .flags = CLK_SET_PARENT_GATE,
434 .flags = CLK_SET_PARENT_GATE,
485 .flags = CLK_SET_PARENT_GATE,
534 .flags = CLK_SET_PARENT_GATE,
583 .flags = CLK_SET_PARENT_GATE,
[all …]
A Dgcc-msm8960.c354 .flags = CLK_SET_PARENT_GATE,
405 .flags = CLK_SET_PARENT_GATE,
456 .flags = CLK_SET_PARENT_GATE,
507 .flags = CLK_SET_PARENT_GATE,
558 .flags = CLK_SET_PARENT_GATE,
609 .flags = CLK_SET_PARENT_GATE,
660 .flags = CLK_SET_PARENT_GATE,
711 .flags = CLK_SET_PARENT_GATE,
760 .flags = CLK_SET_PARENT_GATE,
809 .flags = CLK_SET_PARENT_GATE,
[all …]
A Dgcc-mdm9615.c212 .flags = CLK_SET_PARENT_GATE,
263 .flags = CLK_SET_PARENT_GATE,
314 .flags = CLK_SET_PARENT_GATE,
365 .flags = CLK_SET_PARENT_GATE,
416 .flags = CLK_SET_PARENT_GATE,
479 .flags = CLK_SET_PARENT_GATE,
528 .flags = CLK_SET_PARENT_GATE,
577 .flags = CLK_SET_PARENT_GATE,
626 .flags = CLK_SET_PARENT_GATE,
675 .flags = CLK_SET_PARENT_GATE,
[all …]
A Dgcc-ipq806x.c368 .flags = CLK_SET_PARENT_GATE,
419 .flags = CLK_SET_PARENT_GATE,
470 .flags = CLK_SET_PARENT_GATE,
521 .flags = CLK_SET_PARENT_GATE,
572 .flags = CLK_SET_PARENT_GATE,
623 .flags = CLK_SET_PARENT_GATE,
687 .flags = CLK_SET_PARENT_GATE,
736 .flags = CLK_SET_PARENT_GATE,
785 .flags = CLK_SET_PARENT_GATE,
834 .flags = CLK_SET_PARENT_GATE,
[all …]
/linux/drivers/clk/at91/
A Dsama7g5.c230 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
247 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
264 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
273 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
291 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
A Dclk-smd.c124 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in at91sam9x5_clk_register_smd()
A Dclk-audio-pll.c497 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | in at91_clk_register_audio_pll_pad()
528 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | in at91_clk_register_audio_pll_pmc()
A Dclk-programmable.c238 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in at91_clk_register_programmable()
A Dsam9x60.c262 CLK_SET_PARENT_GATE | in sam9x60_pmc_setup()
A Dclk-generated.c334 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in at91_clk_register_generated()
A Dclk-usb.c240 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | in _at91sam9x5_clk_register_usb()
A Dclk-peripheral.c469 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | in at91_clk_register_sam9x5_peripheral()
A Dclk-main.c568 init.flags = CLK_SET_PARENT_GATE; in at91_clk_register_sam9x5_main()
A Dclk-master.c934 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in at91_clk_sama7g5_register_master()
/linux/drivers/clk/microchip/
A Dclk-pic32mzda.c53 .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,\
/linux/drivers/clk/
A Dclk-axi-clkgen.c546 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in axi_clkgen_probe()
A Dclk.c1988 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) { in clk_calc_new_rates()
2525 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) in clk_core_set_parent_nolock()
3126 ENTRY(CLK_SET_PARENT_GATE),
/linux/drivers/clk/zynqmp/
A Dclkc.c281 ccf_flag |= CLK_SET_PARENT_GATE; in zynqmp_clk_map_common_ccf_flags()
/linux/drivers/clk/ingenic/
A Dcgu.c731 clk_init.flags |= CLK_SET_PARENT_GATE; in ingenic_register_clock()
/linux/include/linux/
A Dclk-provider.h20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ macro

Completed in 60 milliseconds

12