Home
last modified time | relevance | path

Searched refs:CLK_SET_RATE_PARENT (Results 1 – 25 of 299) sorted by relevance

12345678910>>...12

/linux/drivers/clk/hisilicon/
A Dclk-hi3670.c81 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
83 CLK_SET_RATE_PARENT, 0x0, 3, 0, },
85 CLK_SET_RATE_PARENT, 0x0, 27, 0, },
103 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
105 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
107 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
109 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
111 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
165 CLK_SET_RATE_PARENT, 0x0, 5, 0, },
269 CLK_SET_RATE_PARENT, 0, 1, 0, },
[all …]
A Dclk-hi3660.c53 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
55 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
57 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
59 CLK_SET_RATE_PARENT, 0x0, 31, 0, },
61 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
63 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
65 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
67 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
69 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
71 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
[all …]
A Dclk-hi6220.c170 { HI6220_CLK_BUS, "clk_bus", "clk_300m", CLK_SET_RATE_PARENT, 0x490, 0, 4, 7, },
171 { HI6220_MMC0_DIV, "mmc0_div", "mmc0_syspll", CLK_SET_RATE_PARENT, 0x494, 0, 6, 7, },
172 { HI6220_MMC1_DIV, "mmc1_div", "mmc1_syspll", CLK_SET_RATE_PARENT, 0x498, 0, 6, 7, },
173 { HI6220_MMC2_DIV, "mmc2_div", "mmc2_syspll", CLK_SET_RATE_PARENT, 0x49c, 0, 6, 7, },
174 { HI6220_HIFI_DIV, "hifi_div", "hifi_sel", CLK_SET_RATE_PARENT, 0x4a0, 0, 4, 7, },
175 { HI6220_BBPPLL0_DIV, "bbppll0_div", "bbppll_sel", CLK_SET_RATE_PARENT, 0x4a0, 8, 6, 15,},
176 { HI6220_CS_DAPB, "cs_dapb", "picophy_src", CLK_SET_RATE_PARENT, 0x4a0, 24, 2, 31,},
177 { HI6220_CS_ATB_DIV, "cs_atb_div", "cs_atb_syspll", CLK_SET_RATE_PARENT, 0x4a4, 0, 4, 7, },
267 { HI6220_DDRC_SRC, "ddrc_src", "ddr_sel_src", CLK_SET_RATE_PARENT, 0x5a8, 0, 4, 0, },
268 { HI6220_DDRC_AXI1, "ddrc_axi1", "ddrc_src", CLK_SET_RATE_PARENT, 0x5a8, 8, 2, 0, },
[all …]
A Dclk-hi3620.c134 { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, },
135 { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 1, 0, },
136 { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, },
137 { HI3620_TIMER_RCLK23, "timer_rclk23", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 3, 0, },
138 { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
139 { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, },
140 { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, },
141 { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, },
167 { HI3620_TIMERCLK45, "timerclk45", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 3, 0, },
168 { HI3620_TIMERCLK67, "timerclk67", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 4, 0, },
[all …]
A Dcrg-hi3798cv200.c103 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
106 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
108 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
166 CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
168 CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
170 CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
172 CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
174 CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
176 CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
179 CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
[all …]
A Dclk-hi3559a.c187 CLK_SET_RATE_PARENT, 0x170, 1, 0,
191 CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
195 CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
199 CLK_SET_RATE_PARENT, 0x214, 28, 0,
203 CLK_SET_RATE_PARENT, 0x23c, 28, 0,
207 CLK_SET_RATE_PARENT, 0x198, 23, 0,
319 CLK_SET_RATE_PARENT, 0x16c, 6, 0,
323 CLK_SET_RATE_PARENT, 0x16c, 5, 0,
327 CLK_SET_RATE_PARENT, 0x16c, 9, 0,
331 CLK_SET_RATE_PARENT, 0x16c, 8, 0,
[all …]
A Dclk-hix5hd2.c73 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
78 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
80 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
85 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
87 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
94 CLK_SET_RATE_PARENT, 0x120, 0, 0, },
97 CLK_SET_RATE_PARENT, 0x178, 0, 0, },
102 CLK_SET_RATE_PARENT, 0x06c, 4, 0, },
106 CLK_SET_RATE_PARENT, 0x06c, 8, 0, },
110 CLK_SET_RATE_PARENT, 0x06c, 12, 0, },
[all …]
A Dcrg-hi3516cv300.c70 CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
72 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
74 CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
76 CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
78 CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
80 CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
82 CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
94 { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
96 { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
99 { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
[all …]
/linux/drivers/clk/mmp/
A Dclk-of-mmp2.c202 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
209 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
214 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
342 CLK_SET_RATE_PARENT, APMU_GPU, 4, 2, 0, &gpu_lock},
344 CLK_SET_RATE_PARENT, APMU_GPU, 6, 2, 0, &gpu_lock},
346 CLK_SET_RATE_PARENT, APMU_GPU, 12, 2, 0, &gpu_lock},
404 CLK_SET_RATE_PARENT, in mmp2_axi_periph_clk_init()
410 CLK_SET_RATE_PARENT, in mmp2_axi_periph_clk_init()
417 CLK_SET_RATE_PARENT, in mmp2_axi_periph_clk_init()
442 CLK_SET_RATE_PARENT, in mmp2_axi_periph_clk_init()
[all …]
A Dclk-of-pxa168.c106 CLK_SET_RATE_PARENT, in pxa168_pll_init()
145 …{PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
148 …{PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_…
149 …{PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_…
150 …{PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_…
151 …{PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_…
156 …{PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_…
157 …{PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_…
158 …{PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_…
198 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
[all …]
A Dclk-of-pxa910.c106 CLK_SET_RATE_PARENT, in pxa910_pll_init()
143 …{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
146 …{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_…
147 …{PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_…
148 …{PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_…
149 …{PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_…
153 …{PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_…
154 …{PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_…
204 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
208 {PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
[all …]
A Dclk-of-pxa1928.c80 CLK_SET_RATE_PARENT, in pxa1928_pll_init()
108 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0…
109 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0…
110 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0…
114 …{PXA1928_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0,…
117 …{PXA1928_CLK_PWM0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0,…
118 …{PXA1928_CLK_PWM1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0,…
119 …{PXA1928_CLK_PWM2, "pwm2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM2 * 4, 0x3, 0x3, 0x0,…
120 …{PXA1928_CLK_PWM3, "pwm3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM3 * 4, 0x3, 0x3, 0x0,…
126 …{PXA1928_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 0x3, 0x3, 0x…
[all …]
A Dclk-mmp2.c119 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
123 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
127 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
135 CLK_SET_RATE_PARENT, 1, 5); in mmp2_clk_init()
139 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
143 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
147 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
151 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
155 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
[all …]
A Dclk-pxa168.c106 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
110 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
114 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
118 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
122 CLK_SET_RATE_PARENT, 1, 3); in pxa168_clk_init()
126 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
130 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
134 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
138 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
146 CLK_SET_RATE_PARENT, 2, 3); in pxa168_clk_init()
[all …]
A Dclk-pxa910.c111 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
115 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
119 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
123 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
127 CLK_SET_RATE_PARENT, 1, 3); in pxa910_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
135 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
139 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
143 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
151 CLK_SET_RATE_PARENT, 2, 3); in pxa910_clk_init()
[all …]
/linux/drivers/clk/rockchip/
A Dclk-rk3308.c199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
227 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
263 MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, CLK_SET_RATE_PARENT,
267 MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT,
284 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
[all …]
A Dclk-px30.c209 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
221 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
225 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
229 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
233 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
237 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
241 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
475 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
488 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
500 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
[all …]
/linux/drivers/clk/qcom/
A Dgcc-ipq8074.c426 .flags = CLK_SET_RATE_PARENT,
473 .flags = CLK_SET_RATE_PARENT,
506 .flags = CLK_SET_RATE_PARENT,
540 .flags = CLK_SET_RATE_PARENT,
554 .flags = CLK_SET_RATE_PARENT,
587 .flags = CLK_SET_RATE_PARENT,
619 .flags = CLK_SET_RATE_PARENT,
654 .flags = CLK_SET_RATE_PARENT,
1277 .flags = CLK_SET_RATE_PARENT,
1316 .flags = CLK_SET_RATE_PARENT,
[all …]
A Dcamcc-sm8250.c89 .flags = CLK_SET_RATE_PARENT,
112 .flags = CLK_SET_RATE_PARENT,
163 .flags = CLK_SET_RATE_PARENT,
214 .flags = CLK_SET_RATE_PARENT,
265 .flags = CLK_SET_RATE_PARENT,
316 .flags = CLK_SET_RATE_PARENT,
413 .flags = CLK_SET_RATE_PARENT,
435 .flags = CLK_SET_RATE_PARENT,
456 .flags = CLK_SET_RATE_PARENT,
471 .flags = CLK_SET_RATE_PARENT,
[all …]
A Dmmcc-msm8996.c284 .flags = CLK_SET_RATE_PARENT,
314 .flags = CLK_SET_RATE_PARENT,
340 .flags = CLK_SET_RATE_PARENT,
366 .flags = CLK_SET_RATE_PARENT,
392 .flags = CLK_SET_RATE_PARENT,
418 .flags = CLK_SET_RATE_PARENT,
444 .flags = CLK_SET_RATE_PARENT,
470 .flags = CLK_SET_RATE_PARENT,
660 .flags = CLK_SET_RATE_PARENT,
674 .flags = CLK_SET_RATE_PARENT,
[all …]
A Dmmcc-apq8084.c575 .flags = CLK_SET_RATE_PARENT,
589 .flags = CLK_SET_RATE_PARENT,
840 .flags = CLK_SET_RATE_PARENT,
853 .flags = CLK_SET_RATE_PARENT,
891 .flags = CLK_SET_RATE_PARENT,
960 .flags = CLK_SET_RATE_PARENT,
1109 .flags = CLK_SET_RATE_PARENT,
1126 .flags = CLK_SET_RATE_PARENT,
1143 .flags = CLK_SET_RATE_PARENT,
1160 .flags = CLK_SET_RATE_PARENT,
[all …]
A Dgcc-msm8996.c228 .flags = CLK_SET_RATE_PARENT,
243 .flags = CLK_SET_RATE_PARENT,
1279 .flags = CLK_SET_RATE_PARENT,
1294 .flags = CLK_SET_RATE_PARENT,
1309 .flags = CLK_SET_RATE_PARENT,
1337 .flags = CLK_SET_RATE_PARENT,
1352 .flags = CLK_SET_RATE_PARENT,
1367 .flags = CLK_SET_RATE_PARENT,
2693 .flags = CLK_SET_RATE_PARENT,
2720 .flags = CLK_SET_RATE_PARENT,
[all …]
A Dgcc-ipq6018.c78 .flags = CLK_SET_RATE_PARENT,
92 .flags = CLK_SET_RATE_PARENT,
136 .flags = CLK_SET_RATE_PARENT,
167 .flags = CLK_SET_RATE_PARENT,
198 .flags = CLK_SET_RATE_PARENT,
249 .flags = CLK_SET_RATE_PARENT,
280 .flags = CLK_SET_RATE_PARENT,
359 .flags = CLK_SET_RATE_PARENT,
412 .flags = CLK_SET_RATE_PARENT,
713 .flags = CLK_SET_RATE_PARENT,
[all …]
A Dgcc-sc8180x.c281 .flags = CLK_SET_RATE_PARENT,
304 .flags = CLK_SET_RATE_PARENT,
330 .flags = CLK_SET_RATE_PARENT,
354 .flags = CLK_SET_RATE_PARENT,
369 .flags = CLK_SET_RATE_PARENT,
384 .flags = CLK_SET_RATE_PARENT,
399 .flags = CLK_SET_RATE_PARENT,
414 .flags = CLK_SET_RATE_PARENT,
440 .flags = CLK_SET_RATE_PARENT,
461 .flags = CLK_SET_RATE_PARENT,
[all …]
A Dgcc-msm8916.c986 .flags = CLK_SET_RATE_PARENT,
1043 .flags = CLK_SET_RATE_PARENT,
1232 .flags = CLK_SET_RATE_PARENT,
1249 .flags = CLK_SET_RATE_PARENT,
1311 .flags = CLK_SET_RATE_PARENT,
1342 .flags = CLK_SET_RATE_PARENT,
1373 .flags = CLK_SET_RATE_PARENT,
1408 .flags = CLK_SET_RATE_PARENT,
1425 .flags = CLK_SET_RATE_PARENT,
1464 .flags = CLK_SET_RATE_PARENT,
[all …]

Completed in 108 milliseconds

12345678910>>...12