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Searched refs:CLK_SSS (Results 1 – 14 of 14) sorted by relevance

/linux/include/dt-bindings/clock/
A Dexynos5410.h62 #define CLK_SSS 471 macro
A Dexynos5250.h151 #define CLK_SSS 348 macro
A Dexynos4.h93 #define CLK_SSS 255 macro
A Dexynos5420.h168 #define CLK_SSS 471 macro
/linux/Documentation/devicetree/bindings/rng/
A Dsamsung,exynos4-rng.yaml43 clocks = <&clock CLK_SSS>;
A Dsamsung,exynos5250-trng.yaml42 clocks = <&clock CLK_SSS>;
/linux/arch/arm/boot/dts/
A Dexynos5410.dtsi328 clocks = <&clock CLK_SSS>;
372 clocks = <&clock CLK_SSS>;
386 clocks = <&clock CLK_SSS>;
A Dexynos5250.dtsi1187 clocks = <&clock CLK_SSS>;
1232 clocks = <&clock CLK_SSS>;
1237 clocks = <&clock CLK_SSS>;
A Dexynos5420.dtsi1309 clocks = <&clock CLK_SSS>;
1354 clocks = <&clock CLK_SSS>;
1359 clocks = <&clock CLK_SSS>;
A Dexynos4.dtsi1001 clocks = <&clock CLK_SSS>;
1008 clocks = <&clock CLK_SSS>;
/linux/drivers/clk/samsung/
A Dclk-exynos5410.c166 GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
A Dclk-exynos5250.c445 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
A Dclk-exynos4.c894 GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
A Dclk-exynos5420.c930 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),

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