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Searched refs:CLK_TOP_APLL12_DIV0 (Results 1 – 18 of 18) sorted by relevance

/linux/sound/soc/mediatek/mt8183/
A Dmt8183-afe-clk.c44 CLK_TOP_APLL12_DIV0, enumerator
83 [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
514 .div_clk_id = CLK_TOP_APLL12_DIV0,
/linux/include/dt-bindings/clock/
A Dmt8516-clk.h151 #define CLK_TOP_APLL12_DIV0 119 macro
A Dmt6765-clk.h113 #define CLK_TOP_APLL12_DIV0 78 macro
A Dmt6779-clk.h138 #define CLK_TOP_APLL12_DIV0 128 macro
A Dmt8183-clk.h158 #define CLK_TOP_APLL12_DIV0 122 macro
A Dmt8192-clk.h154 #define CLK_TOP_APLL12_DIV0 142 macro
A Dmt8195-clk.h230 #define CLK_TOP_APLL12_DIV0 218 macro
/linux/sound/soc/mediatek/mt8192/
A Dmt8192-afe-clk.h206 CLK_TOP_APLL12_DIV0, enumerator
A Dmt8192-afe-clk.c49 [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
426 .div_clk_id = CLK_TOP_APLL12_DIV0,
/linux/Documentation/devicetree/bindings/sound/
A Dmt8195-afe-pcm.yaml145 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
/linux/drivers/clk/mediatek/
A Dclk-mt8516.c666 GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
A Dclk-mt8195-topckgen.c1158 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, 0x0328, 8, 0),
A Dclk-mt8167.c912 GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
A Dclk-mt6779.c828 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
A Dclk-mt8183.c736 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
A Dclk-mt8192.c861 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0),
A Dclk-mt6765.c531 GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
/linux/arch/arm64/boot/dts/mediatek/
A Dmt8183.dtsi1163 <&topckgen CLK_TOP_APLL12_DIV0>,

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