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Searched refs:CLK_TOP_APLL12_DIV4 (Results 1 – 15 of 15) sorted by relevance

/linux/sound/soc/mediatek/mt8183/
A Dmt8183-afe-clk.c48 CLK_TOP_APLL12_DIV4, enumerator
87 [CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
530 .div_clk_id = CLK_TOP_APLL12_DIV4,
/linux/include/dt-bindings/clock/
A Dmt8516-clk.h155 #define CLK_TOP_APLL12_DIV4 123 macro
A Dmt6779-clk.h142 #define CLK_TOP_APLL12_DIV4 132 macro
A Dmt8183-clk.h162 #define CLK_TOP_APLL12_DIV4 126 macro
A Dmt8192-clk.h158 #define CLK_TOP_APLL12_DIV4 146 macro
A Dmt8195-clk.h234 #define CLK_TOP_APLL12_DIV4 222 macro
/linux/sound/soc/mediatek/mt8192/
A Dmt8192-afe-clk.h210 CLK_TOP_APLL12_DIV4, enumerator
A Dmt8192-afe-clk.c53 [CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
478 .div_clk_id = CLK_TOP_APLL12_DIV4,
/linux/drivers/clk/mediatek/
A Dclk-mt8516.c670 GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
A Dclk-mt8195-topckgen.c1162 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "top_aud_iec_clk", 0x0320, 4, 0x0334, 8, 0),
A Dclk-mt8167.c916 GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
A Dclk-mt6779.c836 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
A Dclk-mt8183.c744 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel",
A Dclk-mt8192.c865 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0),
/linux/arch/arm64/boot/dts/mediatek/
A Dmt8183.dtsi1167 <&topckgen CLK_TOP_APLL12_DIV4>,

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