Searched refs:CLK_TOP_APLL1_DIV4 (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
A D	mt8173-clk.h	135 #define CLK_TOP_APLL1_DIV4 125 macro
/linux/drivers/clk/mediatek/
A D	clk-mt8173.c	599 DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),

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