Searched refs:CLK_TOP_APLL2_DIV1 (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
A D	mt8173-clk.h	138 #define CLK_TOP_APLL2_DIV1 128 macro
/linux/drivers/clk/mediatek/
A D	clk-mt8173.c	603 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),

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