Searched refs:CLK_TOP_APLL2_DIV2 (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
A D	mt8173-clk.h	139 #define CLK_TOP_APLL2_DIV2 129 macro
/linux/drivers/clk/mediatek/
A D	clk-mt8173.c	604 DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),

Completed in 9 milliseconds

Last Index update Sat Jun 03 09:59:21 CST 2023