Searched refs:CLK_TOP_ATB_SEL (Results 1 – 12 of 12) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 103 #define CLK_TOP_ATB_SEL 93 macro
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| A D | mt7622-clk.h | 88 #define CLK_TOP_ATB_SEL 76 macro
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| A D | mt6765-clk.h | 136 #define CLK_TOP_ATB_SEL 101 macro
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| A D | mt8173-clk.h | 114 #define CLK_TOP_ATB_SEL 104 macro
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| A D | mt2712-clk.h | 151 #define CLK_TOP_ATB_SEL 120 macro
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| A D | mt8192-clk.h | 42 #define CLK_TOP_ATB_SEL 30 macro
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt7629.c | 532 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
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| A D | clk-mt7622.c | 565 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
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| A D | clk-mt8173.c | 569 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
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| A D | clk-mt8192.c | 778 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
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| A D | clk-mt2712.c | 785 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
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| A D | clk-mt6765.c | 383 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
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Completed in 25 milliseconds