Searched refs:CLK_TOP_AUD_2_SEL (Results 1 – 7 of 7) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt8173-clk.h | 120 #define CLK_TOP_AUD_2_SEL 110 macro
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| A D | mt2712-clk.h | 157 #define CLK_TOP_AUD_2_SEL 126 macro
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| A D | mt8192-clk.h | 60 #define CLK_TOP_AUD_2_SEL 48 macro
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8173.c | 581 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
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| A D | clk-mt8192.c | 819 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
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| A D | clk-mt2712.c | 799 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8173.dtsi | 874 <&topckgen CLK_TOP_AUD_2_SEL>;
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