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Searched refs:CLK_TOP_AUD_K6_SRC_SEL (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmt2701-clk.h139 #define CLK_TOP_AUD_K6_SRC_SEL 128 macro
/linux/drivers/clk/mediatek/
A Dclk-mt2701.c607 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,

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