Searched refs:CLK_TOP_DDRPHYCFG_SEL (Results 1 – 12 of 12) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 94 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
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| A D | mt7629-clk.h | 85 #define CLK_TOP_DDRPHYCFG_SEL 75 macro
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| A D | mt8516-clk.h | 171 #define CLK_TOP_DDRPHYCFG_SEL 139 macro
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| A D | mt7622-clk.h | 70 #define CLK_TOP_DDRPHYCFG_SEL 58 macro
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| A D | mt8173-clk.h | 94 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
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| A D | mt2701-clk.h | 88 #define CLK_TOP_DDRPHYCFG_SEL 77 macro
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt7629.c | 491 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
595 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_topckgen_init()
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| A D | clk-mt7622.c | 519 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
641 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_topckgen_init()
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| A D | clk-mt8173.c | 544 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
832 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_clk_enable_critical()
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| A D | clk-mt8135.c | 381 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
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| A D | clk-mt2701.c | 492 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
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| A D | clk-mt8167.c | 558 MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
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Completed in 21 milliseconds