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Searched refs:CLK_TOP_ETH_SEL (Results 1 – 9 of 9) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmt7629-clk.h86 #define CLK_TOP_ETH_SEL 76 macro
A Dmt8516-clk.h175 #define CLK_TOP_ETH_SEL 143 macro
A Dmt7622-clk.h71 #define CLK_TOP_ETH_SEL 59 macro
/linux/arch/arm/boot/dts/
A Dmt7629.dtsi444 clocks = <&topckgen CLK_TOP_ETH_SEL>,
467 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
/linux/drivers/clk/mediatek/
A Dclk-mt7629.c493 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
A Dclk-mt7622.c521 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
A Dclk-mt8516.c391 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
A Dclk-mt8167.c571 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
/linux/arch/arm64/boot/dts/mediatek/
A Dmt7622.dtsi930 clocks = <&topckgen CLK_TOP_ETH_SEL>,

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