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Searched refs:CLK_TOP_MEM_SEL (Results 1 – 14 of 14) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmt8135-clk.h89 #define CLK_TOP_MEM_SEL 78 macro
A Dmt7629-clk.h84 #define CLK_TOP_MEM_SEL 74 macro
A Dmt7622-clk.h69 #define CLK_TOP_MEM_SEL 57 macro
A Dmt6765-clk.h132 #define CLK_TOP_MEM_SEL 97 macro
A Dmt8173-clk.h93 #define CLK_TOP_MEM_SEL 83 macro
A Dmt2712-clk.h131 #define CLK_TOP_MEM_SEL 100 macro
A Dmt2701-clk.h89 #define CLK_TOP_MEM_SEL 78 macro
/linux/drivers/clk/mediatek/
A Dclk-mt7629.c489 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
594 clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); in mtk_topckgen_init()
A Dclk-mt7622.c517 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
640 clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); in mtk_topckgen_init()
A Dclk-mt8173.c543 MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
831 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]); in mtk_clk_enable_critical()
A Dclk-mt8135.c375 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
A Dclk-mt2701.c490 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
A Dclk-mt2712.c740 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
A Dclk-mt6765.c370 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,

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