Searched refs:CLK_TOP_MM_SEL (Results 1 – 14 of 14) sorted by relevance
| /linux/Documentation/devicetree/bindings/power/ |
| A D | mediatek,power-controller.yaml | 242 clocks = <&topckgen CLK_TOP_MM_SEL>;
248 clocks = <&topckgen CLK_TOP_MM_SEL>,
255 clocks = <&topckgen CLK_TOP_MM_SEL>;
261 clocks = <&topckgen CLK_TOP_MM_SEL>;
268 clocks = <&topckgen CLK_TOP_MM_SEL>,
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| /linux/include/dt-bindings/clock/ |
| A D | mt6765-clk.h | 133 #define CLK_TOP_MM_SEL 98 macro
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| A D | mt8173-clk.h | 95 #define CLK_TOP_MM_SEL 85 macro
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| A D | mt2712-clk.h | 132 #define CLK_TOP_MM_SEL 101 macro
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| A D | mt2701-clk.h | 87 #define CLK_TOP_MM_SEL 76 macro
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8173.dtsi | 468 clocks = <&topckgen CLK_TOP_MM_SEL>;
474 clocks = <&topckgen CLK_TOP_MM_SEL>,
481 clocks = <&topckgen CLK_TOP_MM_SEL>;
487 clocks = <&topckgen CLK_TOP_MM_SEL>;
494 clocks = <&topckgen CLK_TOP_MM_SEL>,
987 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
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| A D | mt2712e.dtsi | 285 clocks = <&topckgen CLK_TOP_MM_SEL>,
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| /linux/Documentation/devicetree/bindings/soc/mediatek/ |
| A D | scpsys.txt | 67 <&topckgen CLK_TOP_MM_SEL>;
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt2701.c | 494 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
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| A D | clk-mt8173.c | 545 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
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| A D | clk-mt2712.c | 742 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
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| A D | clk-mt6765.c | 373 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
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| /linux/arch/arm/boot/dts/ |
| A D | mt2701.dtsi | 156 clocks = <&topckgen CLK_TOP_MM_SEL>,
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| A D | mt7623.dtsi | 278 clocks = <&topckgen CLK_TOP_MM_SEL>,
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