Searched refs:CLK_TOP_MSDC30_1_SEL (Results 1 – 19 of 19) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 81 #define CLK_TOP_MSDC30_1_SEL 70 macro
|
| A D | mt7629-clk.h | 96 #define CLK_TOP_MSDC30_1_SEL 86 macro
|
| A D | mt7622-clk.h | 81 #define CLK_TOP_MSDC30_1_SEL 69 macro
|
| A D | mt6765-clk.h | 145 #define CLK_TOP_MSDC30_1_SEL 110 macro
|
| A D | mt8173-clk.h | 107 #define CLK_TOP_MSDC30_1_SEL 97 macro
|
| A D | mt2712-clk.h | 144 #define CLK_TOP_MSDC30_1_SEL 113 macro
|
| A D | mt2701-clk.h | 102 #define CLK_TOP_MSDC30_1_SEL 91 macro
|
| A D | mt8192-clk.h | 37 #define CLK_TOP_MSDC30_1_SEL 25 macro
|
| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8135.c | 364 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
|
| A D | clk-mt7629.c | 516 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
|
| A D | clk-mt7622.c | 547 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
|
| A D | clk-mt2701.c | 515 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
|
| A D | clk-mt8173.c | 560 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
|
| A D | clk-mt8192.c | 767 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
|
| A D | clk-mt2712.c | 769 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
|
| A D | clk-mt6765.c | 412 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
|
| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt7622-rfb1.dts | 216 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
|
| A D | mt7622-bananapi-bpi-r64.dts | 239 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
|
| /linux/arch/arm/boot/dts/ |
| A D | mt7623.dtsi | 733 <&topckgen CLK_TOP_MSDC30_1_SEL>;
|
Completed in 36 milliseconds