CLK_TOP_MSDC50_0_H_SEL (reference) in projects: linux

Searched refs:CLK_TOP_MSDC50_0_H_SEL (Results 1 – 6 of 6) sorted by relevance

/linux/include/dt-bindings/clock/
A D	mt8173-clk.h	`105 #define CLK_TOP_MSDC50_0_H_SEL 95 macro`
A D	mt8192-clk.h	`35 #define CLK_TOP_MSDC50_0_H_SEL 23 macro`
/linux/Documentation/devicetree/bindings/mmc/
A D	mtk-sd.yaml	`176 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;`
/linux/drivers/clk/mediatek/
A D	clk-mt8173.c	`558 MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),`
A D	clk-mt8192.c	`762 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",`
/linux/arch/arm64/boot/dts/mediatek/
A D	mt8173.dtsi	`884 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;`

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