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Searched refs:CLK_TOP_MSDC50_2_H_SEL (Results 1 – 3 of 3) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmt8173-clk.h127 #define CLK_TOP_MSDC50_2_H_SEL 117 macro
/linux/drivers/clk/mediatek/
A Dclk-mt8173.c590 MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
/linux/arch/arm64/boot/dts/mediatek/
A Dmt8173.dtsi914 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;

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