Searched refs:CLK_TOP_MSDCPLL_D2 (Results 1 – 21 of 21) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt6797-clk.h | 102 #define CLK_TOP_MSDCPLL_D2 92 macro
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| A D | mt6765-clk.h | 75 #define CLK_TOP_MSDCPLL_D2 40 macro
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| A D | mt8173-clk.h | 48 #define CLK_TOP_MSDCPLL_D2 38 macro
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| A D | mt2712-clk.h | 111 #define CLK_TOP_MSDCPLL_D2 80 macro
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| A D | mt6779-clk.h | 97 #define CLK_TOP_MSDCPLL_D2 87 macro
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| A D | mt8183-clk.h | 122 #define CLK_TOP_MSDCPLL_D2 86 macro
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| A D | mt2701-clk.h | 48 #define CLK_TOP_MSDCPLL_D2 38 macro
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| A D | mt8192-clk.h | 137 #define CLK_TOP_MSDCPLL_D2 125 macro
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| A D | mt8195-clk.h | 203 #define CLK_TOP_MSDCPLL_D2 191 macro
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| /linux/Documentation/devicetree/bindings/mmc/ |
| A D | mtk-sd.yaml | 182 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt6797.c | 83 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
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| A D | clk-mt8195-topckgen.c | 105 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
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| A D | clk-mt2701.c | 98 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
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| A D | clk-mt6779.c | 98 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
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| A D | clk-mt8173.c | 80 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
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| A D | clk-mt8183.c | 158 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
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| A D | clk-mt8192.c | 88 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
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| A D | clk-mt2712.c | 204 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
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| A D | clk-mt6765.c | 124 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8183-kukui.dtsi | 387 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
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| A D | mt8173-elm.dtsi | 383 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
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Completed in 46 milliseconds