Searched refs:CLK_TOP_MUX_AUD_1 (Results 1 – 8 of 8) sorted by relevance
/linux/sound/soc/mediatek/mt8183/ |
A D | mt8183-afe-clk.c | 30 CLK_TOP_MUX_AUD_1, enumerator 69 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1", 240 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret); in apll1_mux_setting() 243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 247 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 282 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 286 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting() 297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 299 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting() [all …]
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/linux/sound/soc/mediatek/mt8192/ |
A D | mt8192-afe-clk.c | 30 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1", 86 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting() 89 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret); in apll1_mux_setting() 92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 96 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 131 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 135 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting() 571 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2; in mt8192_mck_enable()
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A D | mt8192-afe-clk.h | 187 CLK_TOP_MUX_AUD_1, enumerator
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/linux/include/dt-bindings/clock/ |
A D | mt6797-clk.h | 37 #define CLK_TOP_MUX_AUD_1 27 macro
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A D | mt8183-clk.h | 55 #define CLK_TOP_MUX_AUD_1 19 macro
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/linux/drivers/clk/mediatek/ |
A D | clk-mt6797.c | 365 MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
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A D | clk-mt8183.c | 652 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
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/linux/arch/arm64/boot/dts/mediatek/ |
A D | mt8183.dtsi | 1149 <&topckgen CLK_TOP_MUX_AUD_1>,
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