Searched refs:CLK_TOP_SCP_SEL (Results 1 – 13 of 13) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 102 #define CLK_TOP_SCP_SEL 92 macro
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| A D | mt7622-clk.h | 87 #define CLK_TOP_SCP_SEL 75 macro
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| A D | mt6765-clk.h | 134 #define CLK_TOP_SCP_SEL 99 macro
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| A D | mt8173-clk.h | 113 #define CLK_TOP_SCP_SEL 103 macro
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| A D | mt2701-clk.h | 105 #define CLK_TOP_SCP_SEL 94 macro
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| A D | mt8192-clk.h | 14 #define CLK_TOP_SCP_SEL 2 macro
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt7629.c | 529 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
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| A D | clk-mt7622.c | 561 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
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| A D | clk-mt2701.c | 526 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
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| A D | clk-mt8173.c | 568 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
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| A D | clk-mt8192.c | 714 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
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| A D | clk-mt6765.c | 376 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8173.dtsi | 562 clocks = <&topckgen CLK_TOP_SCP_SEL>;
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