Searched refs:CLK_TOP_SPI_SEL (Results 1 – 17 of 17) sorted by relevance
| /linux/Documentation/devicetree/bindings/spi/ |
| A D | spi-mt65xx.txt | 36 The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
63 <&topckgen CLK_TOP_SPI_SEL>,
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| /linux/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 87 #define CLK_TOP_SPI_SEL 76 macro
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| A D | mt8516-clk.h | 189 #define CLK_TOP_SPI_SEL 157 macro
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| A D | mt6765-clk.h | 142 #define CLK_TOP_SPI_SEL 107 macro
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| A D | mt8173-clk.h | 102 #define CLK_TOP_SPI_SEL 92 macro
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| A D | mt2712-clk.h | 139 #define CLK_TOP_SPI_SEL 108 macro
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| A D | mt8192-clk.h | 34 #define CLK_TOP_SPI_SEL 22 macro
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt2712e.dtsi | 555 <&topckgen CLK_TOP_SPI_SEL>,
634 <&topckgen CLK_TOP_SPI_SEL>,
647 <&topckgen CLK_TOP_SPI_SEL>,
660 <&topckgen CLK_TOP_SPI_SEL>,
673 <&topckgen CLK_TOP_SPI_SEL>,
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| A D | mt8516.dtsi | 407 <&topckgen CLK_TOP_SPI_SEL>,
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| A D | mt8173.dtsi | 761 <&topckgen CLK_TOP_SPI_SEL>,
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8135.c | 372 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
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| A D | clk-mt8516.c | 421 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
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| A D | clk-mt8167.c | 611 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
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| A D | clk-mt8173.c | 554 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
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| A D | clk-mt8192.c | 760 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
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| A D | clk-mt2712.c | 758 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
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| A D | clk-mt6765.c | 402 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
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