Searched refs:CLK_TOP_SYSPLL3_D2 (Results 1 – 20 of 20) sorted by relevance
| /linux/Documentation/devicetree/bindings/spi/ |
| A D | spi-mt65xx.txt | 31 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
62 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| /linux/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 43 #define CLK_TOP_SYSPLL3_D2 33 macro
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| A D | mt7622-clk.h | 37 #define CLK_TOP_SYSPLL3_D2 25 macro
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| A D | mt6797-clk.h | 57 #define CLK_TOP_SYSPLL3_D2 47 macro
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| A D | mt6765-clk.h | 46 #define CLK_TOP_SYSPLL3_D2 11 macro
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| A D | mt8173-clk.h | 62 #define CLK_TOP_SYSPLL3_D2 52 macro
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| A D | mt2712-clk.h | 45 #define CLK_TOP_SYSPLL3_D2 14 macro
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| A D | mt2701-clk.h | 23 #define CLK_TOP_SYSPLL3_D2 13 macro
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| /linux/arch/arm/boot/dts/ |
| A D | mt2701.dtsi | 343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
416 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| A D | mt7623.dtsi | 488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
567 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
581 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| A D | mt7629.dtsi | 282 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt7629.c | 411 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
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| A D | clk-mt6797.c | 38 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
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| A D | clk-mt7622.c | 403 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
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| A D | clk-mt2701.c | 70 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
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| A D | clk-mt8173.c | 95 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
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| A D | clk-mt2712.c | 74 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
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| A D | clk-mt6765.c | 93 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt7622.dtsi | 491 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
573 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| A D | mt8173.dtsi | 760 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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