Searched refs:CLK_TOP_SYSPLL4_D2 (Results 1 – 15 of 15) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 46 #define CLK_TOP_SYSPLL4_D2 36 macro
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| A D | mt7622-clk.h | 39 #define CLK_TOP_SYSPLL4_D2 27 macro
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| A D | mt6797-clk.h | 60 #define CLK_TOP_SYSPLL4_D2 50 macro
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| A D | mt6765-clk.h | 49 #define CLK_TOP_SYSPLL4_D2 14 macro
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| A D | mt8173-clk.h | 65 #define CLK_TOP_SYSPLL4_D2 55 macro
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| A D | mt2712-clk.h | 48 #define CLK_TOP_SYSPLL4_D2 17 macro
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| A D | mt2701-clk.h | 25 #define CLK_TOP_SYSPLL4_D2 15 macro
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| /linux/Documentation/devicetree/bindings/spi/ |
| A D | spi-mt65xx.txt | 33 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt7629.c | 414 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
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| A D | clk-mt6797.c | 41 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
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| A D | clk-mt7622.c | 405 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
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| A D | clk-mt2701.c | 72 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
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| A D | clk-mt8173.c | 98 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
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| A D | clk-mt2712.c | 80 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
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| A D | clk-mt6765.c | 96 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
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Completed in 29 milliseconds