Searched refs:CLK_TOP_UART_SEL (Results 1 – 18 of 18) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 88 #define CLK_TOP_UART_SEL 77 macro
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| A D | mt7629-clk.h | 91 #define CLK_TOP_UART_SEL 81 macro
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| A D | mt7622-clk.h | 76 #define CLK_TOP_UART_SEL 64 macro
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| A D | mt6765-clk.h | 141 #define CLK_TOP_UART_SEL 106 macro
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| A D | mt8173-clk.h | 101 #define CLK_TOP_UART_SEL 91 macro
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| A D | mt2712-clk.h | 138 #define CLK_TOP_UART_SEL 107 macro
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| A D | mt2701-clk.h | 98 #define CLK_TOP_UART_SEL 87 macro
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| A D | mt8192-clk.h | 33 #define CLK_TOP_UART_SEL 21 macro
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| /linux/arch/arm/boot/dts/ |
| A D | mt7629.dtsi | 216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt7622.dtsi | 389 clocks = <&topckgen CLK_TOP_UART_SEL>,
400 clocks = <&topckgen CLK_TOP_UART_SEL>,
411 clocks = <&topckgen CLK_TOP_UART_SEL>,
422 clocks = <&topckgen CLK_TOP_UART_SEL>,
587 clocks = <&topckgen CLK_TOP_UART_SEL>,
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8135.c | 373 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
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| A D | clk-mt7629.c | 505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| A D | clk-mt7622.c | 535 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| A D | clk-mt2701.c | 505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| A D | clk-mt8173.c | 553 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
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| A D | clk-mt8192.c | 758 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
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| A D | clk-mt2712.c | 756 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
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| A D | clk-mt6765.c | 399 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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Completed in 34 milliseconds