Searched refs:CLK_TOP_UNIVPLL1_D2 (Results 1 – 19 of 19) sorted by relevance
| /linux/Documentation/devicetree/bindings/spi/ |
| A D | spi-slave-mt27xx.txt | 17 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
32 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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| /linux/arch/arm/boot/dts/ |
| A D | mt7629.dtsi | 101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
325 <&topckgen CLK_TOP_UNIVPLL1_D2>;
393 <&topckgen CLK_TOP_UNIVPLL1_D2>;
469 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
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| /linux/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 43 #define CLK_TOP_UNIVPLL1_D2 32 macro
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| A D | mt7629-clk.h | 50 #define CLK_TOP_UNIVPLL1_D2 40 macro
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| A D | mt7622-clk.h | 44 #define CLK_TOP_UNIVPLL1_D2 32 macro
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| A D | mt6797-clk.h | 68 #define CLK_TOP_UNIVPLL1_D2 58 macro
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| A D | mt6765-clk.h | 58 #define CLK_TOP_UNIVPLL1_D2 23 macro
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| A D | mt8173-clk.h | 73 #define CLK_TOP_UNIVPLL1_D2 63 macro
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| A D | mt2712-clk.h | 57 #define CLK_TOP_UNIVPLL1_D2 26 macro
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| A D | mt2701-clk.h | 36 #define CLK_TOP_UNIVPLL1_D2 26 macro
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8135.c | 61 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
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| A D | clk-mt7629.c | 418 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
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| A D | clk-mt6797.c | 49 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
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| A D | clk-mt7622.c | 410 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
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| A D | clk-mt2701.c | 84 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
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| A D | clk-mt8173.c | 108 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
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| A D | clk-mt2712.c | 98 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
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| A D | clk-mt6765.c | 107 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt2712e.dtsi | 322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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