Searched refs:CLK_TOP_UNIVPLL1_D4 (Results 1 – 17 of 17) sorted by relevance
| /linux/Documentation/devicetree/bindings/spi/ |
| A D | spi-slave-mt27xx.txt | 19 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
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| /linux/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 44 #define CLK_TOP_UNIVPLL1_D4 33 macro
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| A D | mt7629-clk.h | 51 #define CLK_TOP_UNIVPLL1_D4 41 macro
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| A D | mt7622-clk.h | 45 #define CLK_TOP_UNIVPLL1_D4 33 macro
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| A D | mt6797-clk.h | 69 #define CLK_TOP_UNIVPLL1_D4 59 macro
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| A D | mt6765-clk.h | 59 #define CLK_TOP_UNIVPLL1_D4 24 macro
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| A D | mt8173-clk.h | 74 #define CLK_TOP_UNIVPLL1_D4 64 macro
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| A D | mt2712-clk.h | 58 #define CLK_TOP_UNIVPLL1_D4 27 macro
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| A D | mt2701-clk.h | 37 #define CLK_TOP_UNIVPLL1_D4 27 macro
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8135.c | 62 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
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| A D | clk-mt7629.c | 419 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
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| A D | clk-mt6797.c | 50 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
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| A D | clk-mt7622.c | 411 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
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| A D | clk-mt2701.c | 85 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
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| A D | clk-mt8173.c | 109 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
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| A D | clk-mt2712.c | 100 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
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| A D | clk-mt6765.c | 108 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
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