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Searched refs:CLK_TOP_UNIVPLL2_D4 (Results 1 – 20 of 20) sorted by relevance

/linux/Documentation/devicetree/bindings/spi/
A Dspi-slave-mt27xx.txt20 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
A Dspi-mt65xx.txt34 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
/linux/include/dt-bindings/clock/
A Dmt8135-clk.h49 #define CLK_TOP_UNIVPLL2_D4 38 macro
A Dmt7629-clk.h55 #define CLK_TOP_UNIVPLL2_D4 45 macro
A Dmt7622-clk.h49 #define CLK_TOP_UNIVPLL2_D4 37 macro
A Dmt6797-clk.h73 #define CLK_TOP_UNIVPLL2_D4 63 macro
A Dmt6765-clk.h62 #define CLK_TOP_UNIVPLL2_D4 27 macro
A Dmt8173-clk.h78 #define CLK_TOP_UNIVPLL2_D4 68 macro
A Dmt2712-clk.h62 #define CLK_TOP_UNIVPLL2_D4 31 macro
A Dmt2701-clk.h40 #define CLK_TOP_UNIVPLL2_D4 30 macro
/linux/arch/arm/boot/dts/
A Dmt7629.dtsi254 <&topckgen CLK_TOP_UNIVPLL2_D4>;
324 <&topckgen CLK_TOP_UNIVPLL2_D4>,
391 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
/linux/arch/arm64/boot/dts/mediatek/
A Dmt2712e.dtsi554 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
633 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
646 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
659 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
672 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
/linux/drivers/clk/mediatek/
A Dclk-mt8135.c68 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
A Dclk-mt7629.c423 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
A Dclk-mt6797.c54 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
A Dclk-mt7622.c415 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
A Dclk-mt2701.c89 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
A Dclk-mt8173.c113 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
A Dclk-mt2712.c108 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
A Dclk-mt6765.c111 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),

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