/linux/Documentation/devicetree/bindings/media/ |
A D | mediatek-vcodec.txt | 63 <&topckgen CLK_TOP_UNIVPLL_D2>, 84 <&topckgen CLK_TOP_UNIVPLL_D2>,
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/linux/include/dt-bindings/clock/ |
A D | mt8516-clk.h | 51 #define CLK_TOP_UNIVPLL_D2 19 macro
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A D | mt7622-clk.h | 43 #define CLK_TOP_UNIVPLL_D2 31 macro
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A D | mt6797-clk.h | 67 #define CLK_TOP_UNIVPLL_D2 57 macro
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A D | mt6765-clk.h | 57 #define CLK_TOP_UNIVPLL_D2 22 macro
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A D | mt8173-clk.h | 72 #define CLK_TOP_UNIVPLL_D2 62 macro
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A D | mt2712-clk.h | 56 #define CLK_TOP_UNIVPLL_D2 25 macro
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A D | mt6779-clk.h | 70 #define CLK_TOP_UNIVPLL_D2 60 macro
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A D | mt8183-clk.h | 95 #define CLK_TOP_UNIVPLL_D2 59 macro
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A D | mt2701-clk.h | 28 #define CLK_TOP_UNIVPLL_D2 18 macro
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A D | mt8195-clk.h | 154 #define CLK_TOP_UNIVPLL_D2 142 macro
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/linux/drivers/clk/mediatek/ |
A D | clk-mt6797.c | 48 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
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A D | clk-mt7622.c | 409 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
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A D | clk-mt8516.c | 44 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
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A D | clk-mt8195-topckgen.c | 56 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
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A D | clk-mt2701.c | 76 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
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A D | clk-mt8167.c | 48 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
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A D | clk-mt6779.c | 45 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
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A D | clk-mt8173.c | 107 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
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A D | clk-mt8183.c | 72 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
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A D | clk-mt2712.c | 96 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
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A D | clk-mt6765.c | 106 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
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/linux/arch/arm64/boot/dts/mediatek/ |
A D | mt8173.dtsi | 1403 <&topckgen CLK_TOP_UNIVPLL_D2>, 1424 <&topckgen CLK_TOP_UNIVPLL_D2>,
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