Searched refs:CLK_TSADC (Results 1 – 19 of 19) sorted by relevance
/linux/include/dt-bindings/clock/ |
A D | exynos5410.h | 48 #define CLK_TSADC 270 macro
|
A D | s5pv210.h | 154 #define CLK_TSADC 136 macro
|
A D | exynos4.h | 164 #define CLK_TSADC 326 macro
|
A D | exynos5420.h | 79 #define CLK_TSADC 270 macro
|
A D | exynos3250.h | 199 #define CLK_TSADC 193 macro
|
A D | rk3568-cru.h | 336 #define CLK_TSADC 273 macro
|
/linux/Documentation/devicetree/bindings/iio/adc/ |
A D | samsung,exynos-adc.yaml | 157 clocks = <&cmu CLK_TSADC>,
|
/linux/drivers/clk/samsung/ |
A D | clk-exynos5410.c | 209 GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
|
A D | clk-exynos4.c | 943 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15, 970 GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
|
A D | clk-s5pv210.c | 570 GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0),
|
A D | clk-exynos3250.c | 637 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
|
A D | clk-exynos5420.c | 1077 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
|
/linux/arch/arm/boot/dts/ |
A D | exynos5410.dtsi | 256 clocks = <&clock CLK_TSADC>;
|
A D | s5pv210.dtsi | 149 clocks = <&clocks CLK_TSADC>;
|
A D | exynos4412.dtsi | 291 clocks = <&clock CLK_TSADC>;
|
A D | exynos3250.dtsi | 451 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
|
A D | exynos5420.dtsi | 1218 clocks = <&clock CLK_TSADC>;
|
/linux/arch/arm64/boot/dts/rockchip/ |
A D | rk356x.dtsi | 920 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 922 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
/linux/drivers/clk/rockchip/ |
A D | clk-rk3568.c | 1173 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0,
|
Completed in 37 milliseconds