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Searched refs:CONTROL (Results 1 – 25 of 79) sorted by relevance

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/linux/drivers/clocksource/
A Dtimer-digicolor.c51 #define CONTROL(t) ((t)*8) macro
75 writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); in dc_timer_disable()
81 writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); in dc_timer_enable()
183 writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
185 writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
/linux/drivers/parport/
A Dparport_gsc.c84 s->u.pc.ctr = parport_readb (CONTROL (p)); in parport_gsc_save_state()
89 parport_writeb (s->u.pc.ctr, CONTROL (p)); in parport_gsc_restore_state()
148 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
155 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
158 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
159 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
160 parport_writeb (0xc, CONTROL (pb)); in parport_SPP_supported()
A Dparport_gsc.h47 #define CONTROL(p) ((p)->base + 0x2) macro
103 parport_writeb (ctr, CONTROL (p)); in __parport_gsc_frob_control()
A Dparport_pc.c252 outb(c, CONTROL(p)); in parport_pc_restore_state()
1411 outb(w, CONTROL(pb)); in parport_SPP_supported()
1418 r = inb(CONTROL(pb)); in parport_SPP_supported()
1421 outb(w, CONTROL(pb)); in parport_SPP_supported()
1422 r = inb(CONTROL(pb)); in parport_SPP_supported()
1423 outb(0xc, CONTROL(pb)); in parport_SPP_supported()
1482 outb(r, CONTROL(pb)); in parport_ECR_present()
1486 r = inb(CONTROL(pb)); in parport_ECR_present()
1499 outb(0xc, CONTROL(pb)); in parport_ECR_present()
1507 outb(0xc, CONTROL(pb)); in parport_ECR_present()
[all …]
/linux/include/linux/
A Dparport_pc.h15 #define CONTROL(p) ((p)->base + 0x2) macro
86 unsigned char dcr = inb (CONTROL (p)); in dump_parport_state()
100 dcr = i ? priv->ctr : inb (CONTROL (p)); in dump_parport_state()
141 outb (ctr, CONTROL (p)); in __parport_pc_frob_control()
/linux/sound/pci/
A Dens1370.c679 inl(ES_REG(ensoniq, CONTROL)); in snd_es1371_codec_read()
873 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback1_prepare()
892 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback1_prepare()
914 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback2_prepare()
932 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback2_prepare()
954 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_capture_prepare()
970 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_capture_prepare()
1421 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_es1371_spdif_put()
1687 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_control_put()
1818 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_create_gameport()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_optc.c107 REG_UPDATE(CONTROL, in optc31_enable_crtc()
134 REG_UPDATE(CONTROL, in optc31_disable_crtc()
153 REG_UPDATE(CONTROL, in optc31_immediate_disable_crtc()
/linux/drivers/bluetooth/
A Dbt3c_cs.c113 #define CONTROL 4 macro
349 iir = inb(iobase + CONTROL); in bt3c_interrupt()
370 outb(iir, iobase + CONTROL); in bt3c_interrupt()
524 outb(inb(iobase + CONTROL) | 0x40, iobase + CONTROL); in bt3c_load_firmware()
/linux/drivers/watchdog/
A Dmachzwd.c52 #define CONTROL 0x10 /* 16 */ macro
155 return zf_readw(CONTROL); in zf_get_control()
160 zf_writew(CONTROL, new); in zf_set_control()
/linux/drivers/media/usb/uvc/
A Duvc_ctrl.c884 uvc_dbg(chain->dev, CONTROL, "Control 0x%08x not found\n", in uvc_find_control()
1919 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
1932 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
1940 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
1970 uvc_dbg(dev, CONTROL, in uvc_ctrl_init_xu_ctrl()
2001 uvc_dbg(chain->dev, CONTROL, "Extension unit %u not found\n", in uvc_xu_ctrl_query()
2017 uvc_dbg(chain->dev, CONTROL, "Control %pUl/%u not found\n", in uvc_xu_ctrl_query()
2232 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping()
2279 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping()
2290 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping()
[all …]
/linux/drivers/hwmon/
A Dadt7475.c30 #define CONTROL 3 macro
788 data->pwm[CONTROL][sattr->index] = in pwm_store()
795 if (((data->pwm[CONTROL][sattr->index] >> 5) & 7) != 7) { in pwm_store()
906 data->pwm[CONTROL][index] &= ~0xE0; in hw_set_pwm()
907 data->pwm[CONTROL][index] |= (val & 7) << 5; in hw_set_pwm()
910 data->pwm[CONTROL][index]); in hw_set_pwm()
1751 data->pwm[CONTROL][index] = adt7475_read(PWM_CONFIG_REG(index)); in adt7475_read_pwm()
1757 v = (data->pwm[CONTROL][index] >> 5) & 7; in adt7475_read_pwm()
1770 data->pwm[CONTROL][index] &= ~0xE0; in adt7475_read_pwm()
1771 data->pwm[CONTROL][index] |= (7 << 5); in adt7475_read_pwm()
[all …]
/linux/Documentation/devicetree/bindings/timer/
A Dmarvell,orion-timer.txt5 - reg: base address of the timer register starting with TIMERS CONTROL register
/linux/Documentation/leds/
A Dleds-lm3556.rst23 CONTROL REGISTER(0x09).Flash mode is activated by the ENABLE REGISTER(0x0A),
50 In Torch Mode, the current source(LED) is programmed via the CURRENT CONTROL
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_opp.h78 SRI(CONTROL, FMT_MEMORY, id)
82 SRI(CONTROL, FMT_MEMORY, id)
295 uint32_t CONTROL; member
A Ddce_opp.c589 REG_GET(CONTROL, in program_formatter_420_memory()
596 REG_UPDATE(CONTROL, in program_formatter_420_memory()
/linux/net/core/
A Ddevlink.c10498 DEVLINK_TRAP(STP, CONTROL),
10499 DEVLINK_TRAP(LACP, CONTROL),
10500 DEVLINK_TRAP(LLDP, CONTROL),
10506 DEVLINK_TRAP(MLD_QUERY, CONTROL),
10517 DEVLINK_TRAP(IPV4_BFD, CONTROL),
10518 DEVLINK_TRAP(IPV6_BFD, CONTROL),
10521 DEVLINK_TRAP(IPV4_BGP, CONTROL),
10522 DEVLINK_TRAP(IPV6_BGP, CONTROL),
10525 DEVLINK_TRAP(IPV4_PIM, CONTROL),
10526 DEVLINK_TRAP(IPV6_PIM, CONTROL),
[all …]
/linux/drivers/net/ethernet/smsc/
A Dsmc9194.c338 outw( inw( ioaddr + CONTROL ) | CTL_AUTO_RELEASE , ioaddr + CONTROL ); in smc_reset()
398 outw( inw( ioaddr + CONTROL ), CTL_POWERDOWN, ioaddr + CONTROL ); in smc_shutdown()
A Dsmc91c92_cs.c191 #define CONTROL 12 macro
553 outw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL); in mot_setup()
557 wait = ((CTL_RELOAD | CTL_STORE) & inw(ioaddr + CONTROL)); in mot_setup()
775 outw(0, ioaddr + CONTROL); in check_sig()
1105 outw(CTL_POWERDOWN, ioaddr + CONTROL ); in smc_close()
1336 outw(CTL_AUTO_RELEASE | 0x0000, ioaddr + CONTROL); in smc_eph_irq()
1338 ioaddr + CONTROL); in smc_eph_irq()
1664 ioaddr + CONTROL); in smc_reset()
A Dsmc9194.h104 #define CONTROL 12 macro
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_optc.c277 REG_UPDATE(CONTROL, in optc1_program_timing()
368 REG_UPDATE_2(CONTROL, in optc1_set_vtg_params()
372 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); in optc1_set_vtg_params()
512 REG_UPDATE(CONTROL, in optc1_enable_crtc()
540 REG_UPDATE(CONTROL, in optc1_disable_crtc()
/linux/drivers/scsi/
A Daha1542.h29 #define CONTROL(base) STATUS(base) macro
A Daha1542.c78 outb(IRST, CONTROL(base)); in aha1542_intr_reset()
221 outb(SRST | IRST /*|SCRST */ , CONTROL(sh->io_port)); in aha1542_test_port()
255 outb(IRST, CONTROL(sh->io_port)); in aha1542_test_port()
937 outb(reset_cmd, CONTROL(cmd->device->host->io_port)); in aha1542_reset()
/linux/Documentation/devicetree/bindings/iio/amplifiers/
A Dadi,hmc425a.yaml15 HMC425A 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL POSITIVE CONTROL ATTENUATOR, 2.2 - 8.0 GHz
/linux/Documentation/driver-api/backlight/
A Dlp855x-driver.rst44 Value of DEVICE CONTROL register.
/linux/Documentation/devicetree/bindings/leds/backlight/
A Dlp855x.txt7 - dev-ctrl: Value of DEVICE CONTROL register (u8). It depends on the device.

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