Home
last modified time | relevance | path

Searched refs:CORE_MOD (Results 1 – 13 of 13) sorted by relevance

/linux/arch/arm/mach-omap2/
A Domap_hwmod_2xxx_ipblock_data.c204 .module_offs = CORE_MOD,
219 .module_offs = CORE_MOD,
234 .module_offs = CORE_MOD,
249 .module_offs = CORE_MOD,
264 .module_offs = CORE_MOD,
279 .module_offs = CORE_MOD,
294 .module_offs = CORE_MOD,
309 .module_offs = CORE_MOD,
324 .module_offs = CORE_MOD,
339 .module_offs = CORE_MOD,
[all …]
A Domap_hwmod_2430_data.c85 .module_offs = CORE_MOD,
100 .module_offs = CORE_MOD,
115 .module_offs = CORE_MOD,
130 .module_offs = CORE_MOD,
143 .module_offs = CORE_MOD,
175 .module_offs = CORE_MOD,
219 .module_offs = CORE_MOD,
235 .module_offs = CORE_MOD,
251 .module_offs = CORE_MOD,
267 .module_offs = CORE_MOD,
[all …]
A Dcm3xxx.c422 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap3_cm_save_context()
424 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); in omap3_cm_save_context()
438 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); in omap3_cm_save_context()
440 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); in omap3_cm_save_context()
442 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); in omap3_cm_save_context()
464 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); in omap3_cm_save_context()
479 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); in omap3_cm_save_context()
481 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); in omap3_cm_save_context()
483 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); in omap3_cm_save_context()
552 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, in omap3_cm_restore_context()
[all …]
A Dpm24xx.c75 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); in omap2_enter_full_retention()
76 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); in omap2_enter_full_retention()
100 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); in omap2_enter_full_retention()
101 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); in omap2_enter_full_retention()
137 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); in omap2_enter_mpu_retention()
138 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); in omap2_enter_mpu_retention()
A Domap_hwmod_2420_data.c99 .module_offs = CORE_MOD,
119 .module_offs = CORE_MOD,
135 .module_offs = CORE_MOD,
163 .module_offs = CORE_MOD,
179 .module_offs = CORE_MOD,
209 .module_offs = CORE_MOD,
223 .module_offs = CORE_MOD,
A Domap_hwmod_3xxx_data.c261 .module_offs = CORE_MOD,
276 .module_offs = CORE_MOD,
347 .module_offs = CORE_MOD,
362 .module_offs = CORE_MOD,
424 .module_offs = CORE_MOD,
603 .module_offs = CORE_MOD,
618 .module_offs = CORE_MOD,
633 .module_offs = CORE_MOD,
827 .module_offs = CORE_MOD,
891 .module_offs = CORE_MOD,
[all …]
A Dcm2xxx.c328 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap2xxx_cm_fclks_active()
329 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); in omap2xxx_cm_fclks_active()
339 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap2xxx_cm_mpu_retention_allowed()
345 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); in omap2xxx_cm_mpu_retention_allowed()
374 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & in omap2xxx_cm_set_mod_dividers()
376 omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1); in omap2xxx_cm_set_mod_dividers()
A Dprm3xxx.c276 CORE_MOD, OMAP2_RM_RSTCTRL); in omap3_prm_reset_modem()
277 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); in omap3_prm_reset_modem()
353 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); in omap3_prm_init_pm()
354 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); in omap3_prm_init_pm()
361 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); in omap3_prm_init_pm()
A Dpowerdomains3xxx_data.c97 .prcm_offs = CORE_MOD,
114 .prcm_offs = CORE_MOD,
136 .prcm_offs = CORE_MOD,
A Dpowerdomains2xxx_data.c58 .prcm_offs = CORE_MOD,
A Dpm34xx.c146 c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0); in _prcm_int_handle_wakeup()
149 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0); in _prcm_int_handle_wakeup()
A Dsleep34xx.S29 #define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
32 #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
A Dprcm-common.h24 #define CORE_MOD 0x200 macro

Completed in 20 milliseconds